SPI Interface, Low CON and QINJ, ±15 V/+12 V,
1.8 V Logic Control, 8:1/Dual 4:1 Mux Switches
SPI interface with error detection
Includes CRC, invalid read/write address, and SCLK count
Supports burst mode and daisy-chain mode
Industry standard SPI Mode 0 and SPI Mode 3 interface
Round robin mode allows switching times that are
comparable with a parallel interface
Four general-purpose digital outputs that can be used to
control other devices
<1 pC charge injection over full signal range
1 pF off capacitance
VSS to VDD analog signal range
Fully specified at ±15 V and +12 V
1.8 V logic compatibility with 2.7 V ≤ VL ≤ 3.3 V
24-lead LFCSP package
Audio and video routing
Automatic test equipment
Data acquisition systems
The ADGS1208/ADGS1209 are analog multiplexers comprising
eight single channels and four differential channels, respectively. A
serial peripheral interface (SPI) controls the switches. The SPI
interface has robust error detection features, such as cyclic
redundancy check (CRC) error detection, invalid read/write
address detection, and SCLK count error detection.
It is possible to daisy-chain multiple ADGS1208/ADGS1209
devices together. Daisy-chain mode enables the configuration of
multiple devices with a minimal amount of digital lines. The
ADGS1208/ADGS1209 can also operate in burst mode to
decrease the time between SPI commands.
iCMOS® construction ensures ultralow power dissipation,
making the devices ideally suited for portable and battery-
Each switch conducts equally well in both directions when on,
and each switch has an input signal range that extends to the
supplies. In the off condition, signal levels up to the supplies
FUNCTIONAL BLOCK DIAGRAMS
SCLK SDI CS RESET/VL
Figure 1. ADGS1208 Functional Block Diagram
SCLK SDI CS RESET/VL
Figure 2. ADGS1209 Functional Block Diagram
The ultralow on capacitance (CON) and exceptionally low charge
injection (QINJ) of these multiplexers make them ideal solutions
for data acquisition and sample-and-hold applications, where
low glitch and fast settling are required.
1. SPI interface removes the need for parallel conversion,
logic traces, and reduces GPIO channel count.
2. Daisy-chain mode removes additional logic traces when
multiple devices are used.
3. CRC error detection, invalid read/write address detection,
and SCLK count error detection ensure a robust digital
4. CRC and error detection capabilities allow the use of the
ADGS1208/ADGS1209 in safety critical systems.
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