ADSP-21369 - SHARC Processor

Analog Devices

Datasheet Details

3 SHARC Family Core Architecture 4 Family Peripheral Architecture 7 I/O Processor

include JTAG access to memory permitted with a 64-bit key Protected memory regions that can be assigned to limit access under program control to sensitive code PLL has a wide variety of software and hardware multi- plier/divider ratios Available in 256-ball BGA_ED and 208-lead LQFP_EP packages SIMD Core Instruction Cache 5 stage Sequencer DAG1/2 Timer PEx PEy FLAGx/IRQx/ TMREXP JTAG Block 0 RAM/ROM Internal Memory Block 1 RAM/ROM Block 2 RAM Block 3 RAM DMD 64-BIT S DMD 64-BIT P.

📁 ADSP-21369 Similar Datasheet

Other Datasheets by Analog Devices

Published: Jul 11, 2019 |