ADSP-TS101S datasheet, processor equivalent, Analog Devices

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ADSP-TS101S Features and benefits

300 MHz, 3.3 ns Instruction Cycle Rate 6M Bits of Internal—On-Chip—SRAM Memory 19 mm ؋ 19 mm (484-Ball) or 27 mm ؋ 27 mm (625-Ball) PBGA Package Dual Computation Blocks—E.

ADSP-TS101S Application

Performs Exceptionally Well on DSP Algorithm and I/O Benchmarks (See Benchmarks in Table 1 and Table 2) Supports Low Ove.

ADSP-TS101S Description

GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . 2 Dual Compute Blocks . . . . . . . . . . . . . . . . . . . . . . . . 3 Data Alignment Buffer (DAB) . . . . . . . . . . . . . . . . . . 4 Dual Integer ALUs (IALUs) . . . . . . . . . . . . ..

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