* 25 MIPS, 40 ns Maximum Instruction Rate Separate On-Chip Buses for Program and Data Memory Program Memory Stores Both Instructions and Data (Three-Bus Performance) Dual Data Address Generators with Modulo and Bit-Reverse Addressing Efficient Program Sequencing with Zero-Overhead Looping: Single-Cycl
ADSP2101BP100 Datasheet (Direct Link)
ADSP2101BP100
Direct Link
Adsp-2100 family dsp microcomputers.
a ADSP-2100 Family DSP Microcomputers ADSP-21xx SUMMARY 16-Bit Fixed-Point DSP Microprocessors with On-Chip Memory Enhanced Harvard Architecture fo.
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