ADSP21065L Description
a SUMMARY High Performance Signal puter for munications, Audio, Automotive, Instrumentation and Industrial Applications Super Harvard Architecture puter (SHARC®) Four Independent Buses for Dual Data, Instruction, and I/O Fetch on a Single Cycle 32-Bit Fixed-Point Arithmetic; 32-Bit and 40-Bit FloatingPoint Arithmetic 544 Kbits On-Chip SRAM Memory and Integrated I/O Peripheral I2S Support, for Eight Simultaneous...