Datasheet Summary
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SUMMARY High Performance Signal puter for munications, Audio, Automotive, Instrumentation and Industrial Applications Super Harvard Architecture puter (SHARC®) Four Independent Buses for Dual Data, Instruction, and I/O Fetch on a Single Cycle 32-Bit Fixed-Point Arithmetic; 32-Bit and 40-Bit FloatingPoint Arithmetic 544 Kbits On-Chip SRAM Memory and Integrated I/O Peripheral I2S Support, for Eight Simultaneous Receive and Transmit Channels KEY Features
66 MIPS, 198 MFLOPS Peak, 132 MFLOPS Sustained Performance User-Configurable 544 Kbits On-Chip SRAM Memory Two External Port, DMA Channels and Eight Serial Port, DMA Channels
DSP Microputer ADSP-21065L
SDRAM Controller for...