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Arizona Microtek

AZ100LVE111 Datasheet Preview

AZ100LVE111 Datasheet

ECL/PECL 1:9 Differential Clock Driver

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ARIZONA MICROTEK, INC.
AZ10LVE111
AZ100LVE111
ECL/PECL 1:9 Differential Clock Driver
FEATURES
Operating Range of 3.0V to 5.5V
Low Skew
Guaranteed Skew Spec
Differential Design
VBB Output
75kΩ Internal Pulldown Resistors
Direct Replacement for ON
Semiconductor MC100LVE111
DESCRIPTION
PACKAGE AVAILABILITY
PACKAGE
PART NO.
MARKING NOTES
PLCC 28
AZ10LVE111FN
AZ10
LVE111
<Date Code>
1,2
PLCC 28
AZ100LVE111FN
AZ100
LVE111
<Date Code>
1,2
PLCC 28 RoHS
Compliant / Lead
(Pb) Free
AZ100LVE111FN+
AZ100+
LVE111
<Date Code>
1,2
1 Add R2 at end of part number for 13 inch (750 parts) Tape & Reel.
2 Date code format: “YY” for year followed by “WW” for week.
The AZ10/100LVE111 is a low skew 1-to-9 differential driver, designed with clock distribution in mind. The
IN signal is fanned-out to nine identical differential outputs.
The AZ100LVE111 provides a VBB output for single-ended use or a DC bias reference for AC coupling to the
device. For single–ended input applications, the VBB reference should be connected to one side of the IN/I¯N¯
differential input pair. The input signal is then fed to the other IN/I¯N¯ input. When used, the VBB pin should be
bypassed to ground via a 0.01μF capacitor.
The device is specifically designed, modeled and produced with low skew as the key goal. Optimal design and
layout serve to minimize gate-to-gate skew within-device, and empirical modeling is used to determine process
control limits that ensure consistent tpd distributions from lot-to-lot. The net result is a dependable, guaranteed low
skew device.
To ensure that the tight skew specification is met, both sides of the differential output must be terminated into
50Ω, even if only one side is used. In most applications all nine differential pairs will be used and therefore
terminated. In the case where fewer than nine pairs are used, it is necessary to terminate at least the output pairs on
the same package side (i.e. sharing the same VCCO) as the pair(s) being used on that side, in order to maintain
minimum skew. Failure to do this will result in small degradations of propagation delay (on the order of 10-20ps) of
the output(s) being used that, while not being catastrophic to most designs, will mean a loss of skew margin.
NOTE: Specifications in ECL/PECL tables are valid when thermal equilibrium is established.
1630 S. STAPLEY DR., SUITE 127 MESA, ARIZONA 85204 USA (480) 962-5881 FAX (480) 890-2541
www.azmicrotek.com




Arizona Microtek

AZ100LVE111 Datasheet Preview

AZ100LVE111 Datasheet

ECL/PECL 1:9 Differential Clock Driver

No Preview Available !

AZ10LVE111
AZ100LVE111
VEE
NC
Q0
Q0
Q1 VCCO
Q1
Q2
Q2
25 24 23 22 21 20 19
26 18
27 17
Q3
Q3
IN 28
VCC
IN
1
2
Pinout: 28-Lead
PLCC (top view)
16 Q4
15 VCCO
14 Q4
V
BB
NC
3
4
13 Q5
12 Q5
5 6 7 8 9 10 11
Q8
Q8
Q7 VCCO
Q7
Q6
Q6
IN
IN
PIN DESCRIPTION
PIN
IN, I¯N¯
Q0, Q¯¯0-Q8, Q¯¯8
VBB
VCC , VCCO
VEE
NC
FUNCTION
Differential Input Pair
Differential Outputs
VBB Output
Positive Supply
Negative Supply
No Connect
VBB
LOGIC SYMBOL
Q0
Q0
Q1
Q1
Q2
Q2
Q3
Q3
Q4
Q4
Q5
Q5
Q6
Q6
Q7
Q7
Q8
Q8
Absolute Maximum Ratings are those values beyond which device life may be impaired.
Symbol
Characteristic
Rating
VCC PECL Power Supply (VEE = 0V)
VI PECL Input Voltage (VEE = 0V)
VEE ECL Power Supply (VCC = 0V)
VI ECL Input Voltage (VCC = 0V)
IOUT
Output Current
--- Continuous
--- Surge
0 to +8.0
0 to +6.0
-8.0 to 0
-6.0 to 0
50
100
TA Operating Temperature Range
TSTG Storage Temperature Range
-40 to +85
-65 to +150
Unit
Vdc
Vdc
Vdc
Vdc
mA
°C
°C
10K ECL DC Characteristics (VEE = -3.0V to -5.5V, VCC = VCCO = GND)
Symbol
Characteristic
-40°C
0°C
Min Typ Max Min Typ Max
VOH Output HIGH Voltage1 -1080
VOL Output LOW Voltage1 -1950
-890 -1020
-1650 -1950
-840
-1630
VIH
Input HIGH Voltage
-1230
-890 -1170
-840
VIL
Input LOW Voltage
-1950
-1500 -1950
-1480
VBB
Reference Voltage
-1430
-1300 -1380
-1270
IIH Input HIGH Current
150 150
IIL
Input LOW Current
0.5
0.5
IEE Power Supply Current
48 60
48 60
1. Each output is terminated through a 50Ω resistor to VCC – 2V.
Min
-980
-1950
-1130
-1950
-1350
0.5
25°C
Typ
48
Max
-810
-1630
-810
-1480
-1250
150
60
Min
-910
-1950
-1060
-1950
-1310
0.5
85°C
Typ
48
Max
-720
-1595
-720
-1445
-1190
150
60
November 2006 * REV - 5
www.azmicrotek.com
2
Unit
mV
mV
mV
mV
mV
μA
μA
mA


Part Number AZ100LVE111
Description ECL/PECL 1:9 Differential Clock Driver
Maker Arizona Microtek
Total Page 6 Pages
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