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Arizona Microtek

AZ100LVE210 Datasheet Preview

AZ100LVE210 Datasheet

ECL/PECL 1:4 / 1:5 Differential Clock Driver

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ARIZONA MICROTEK, INC.
AZ100LVE210
ECL/PECL 1:4, 1:5 Differential Clock Driver
FEATURES
PACKAGE AVAILABILITY
Operating Range of 3.0V to 5.5V
Low Skew
PACKAGE PART NUMBER MARKING NOTES
Guaranteed Skew Spec
Differential Design
VBB Output
75kΩ Internal Input Pulldown Resistors
PLCC 28
AZ100LVE210FN
AZM100LVE210
<Date Code>
1,2
1 Add R2 at end of part number for 13 inch (2.5K parts) Tape & Reel.
2 Date code format: “YY” for year followed by “WW” for week.
Direct Replacement for ON Semiconductor
MC100LVE210 & MC100E210
DESCRIPTION
The AZ100LVE210 is a low skew 1:4, 1:5 fanout buffer designed with clock distribution in mind. The device
features fully differential clock paths to minimize both device and system skew. The AZ100LVE210 offers two
selectable clock inputs allowing redundant or test clocks to be incorporated into the system clock trees.
The AZ100LVE210 provides a VBB output for single-ended use or a DC bias reference for AC coupling to the
device. For single–ended input applications, the VBB reference should be connected to one side of the CLKa/CLKb
differential input pair. The input signal is then fed to the other CLKa/CLKb input. The VBB should only be used as a
bias for its sink/source capability is limited. When used, the VBB pin should be bypassed to ground via a 0.01μF
capacitor.
Both sides of the differential output must be terminated into 50Ω to ensure that the tight skew specification is
met, even if only one side is used. In most applications all eight differential pairs will be used and therefore
terminated. In the case where fewer than eight pairs are used, all output pairs on the same package side (sharing the
same VCCO) as the pairs being used should be terminated to maintain minimum skew. Failure to do this will result in
small degradations of propagation delay (on the order of 10–20ps) of the outputs being used; while not being
catastrophic to most designs this will result in an increase in skew.
NOTE: Specifications in the ECL/PECL tables are valid when thermal equilibrium is established.
1630 S. STAPLEY DR., SUITE 127 MESA, ARIZONA 85204 USA (480) 962-5881 FAX (480) 890-2541
www.azmicrotek.com




Arizona Microtek

AZ100LVE210 Datasheet Preview

AZ100LVE210 Datasheet

ECL/PECL 1:4 / 1:5 Differential Clock Driver

No Preview Available !

AZ100LVE210
Qa0 Qa0 Qa1 VCCO Qa1 Qa2
25 24 23 22 21 20
VEE 26
Qa2
19
18 Qa3
VBB 27
17 Qa3
CLKa 28
VCC 1
CLKa
2
Pinout: 28-Lead
PLCC (top view)
16 Qb0
15 VCCO
14 Qb0
CLKb 3
13 Qb1
CLKb
4 12 Qb1
5 6 7 8 9 10 11
Qb4 Qb4 Qb3 VCCO Qb3 Qb2 Qb2
PIN DESCRIPTION
PIN
CLKa, C¯L¯¯Ka
CLKb,C¯L¯¯Kb
Qa0, Q¯ a0 - Qa3, Q¯ a3
Qb0, Q¯ b0 - Qb4, Q¯ b4
VBB
VCC , VCCO
VEE
FUNCTION
Differential Input Pairs
Differential Input Pairs
Differential Output Pairs
Differential Output Pairs
VBB Output
Positive Supply
Negative Supply
CLKa
CLKa
CLKb
CLKb
LOGIC SYMBOL
VBB
Qa0
Qa0
Qa1
Qa1
Qa2
Qa2
Qa3
Qa3
Qb0
Qb0
Qb1
Qb1
Qb2
Qb2
Qb3
Qb3
Qb4
Qb4
Absolute Maximum Ratings are those values beyond which device life may be impaired.
Symbol
Characteristic
Rating
VCC PECL Power Supply (VEE = 0V)
VI PECL Input Voltage (VEE = 0V)
VEE ECL Power Supply (VCC = 0V)
VI ECL Input Voltage (VCC = 0V)
IOUT
Output Current
--- Continuous
--- Surge
0 to +8.0
0 to +6.0
-8.0 to 0
-6.0 to 0
50
100
TA Operating Temperature Range
TSTG Storage Temperature Range
-40 to +85
-65 to +150
Unit
Vdc
Vdc
Vdc
Vdc
mA
°C
°C
100K ECL DC Characteristics (VEE = -3.0V to -5.5V, VCC = VCCO = GND)
Symbol
Characteristic
-40°C
0°C
Min Typ Max Min Typ Max Min
VOH Output HIGH Voltage1 -1085 -1005 -880 -1025 -955 -880 -1025
VOL Output LOW Voltage1 -1830 -1695 -1555 -1810 -1705 -1620 -1810
VIH
Input HIGH Voltage
-1165
-880 -1165
-880 -1165
VIL
Input LOW Voltage
-1810
-1475 -1810
-1475 -1810
VBB
Reference Voltage
-1380
-1260 -1380
-1260 -1380
IIH Input HIGH Current
150 150
IIL
Input LOW Current
0.5
0.5
0.5
IEE Power Supply Current
55 60
55 60
1. Each output is terminated through a 50Ω resistor to VCC – 2V.
25°C
Typ
-955
-1705
55
Max
-880
-1620
-880
-1475
-1260
150
60
Min
-1025
-1810
-1165
-1810
-1380
0.5
85°C
Typ
-955
-1705
65
Max
-880
-1620
-880
-1475
-1260
150
70
Unit
mV
mV
mV
mV
mV
μA
μA
mA
November 2006 * REV - 4
www.azmicrotek.com
2


Part Number AZ100LVE210
Description ECL/PECL 1:4 / 1:5 Differential Clock Driver
Maker Arizona Microtek
Total Page 5 Pages
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