ARIZONA MICROTEK, INC.
ECL/PECL 1:4, 1:5 Differential Clock Driver
• Operating Range of 3.0V to 5.5V
• Low Skew
PACKAGE PART NUMBER MARKING NOTES
• Guaranteed Skew Spec
• Differential Design
• VBB Output
• 75kΩ Internal Input Pulldown Resistors
1 Add R2 at end of part number for 13 inch (2.5K parts) Tape & Reel.
2 Date code format: “YY” for year followed by “WW” for week.
• Direct Replacement for ON Semiconductor
MC100LVE210 & MC100E210
The AZ100LVE210 is a low skew 1:4, 1:5 fanout buffer designed with clock distribution in mind. The device
features fully differential clock paths to minimize both device and system skew. The AZ100LVE210 offers two
selectable clock inputs allowing redundant or test clocks to be incorporated into the system clock trees.
The AZ100LVE210 provides a VBB output for single-ended use or a DC bias reference for AC coupling to the
device. For single–ended input applications, the VBB reference should be connected to one side of the CLKa/CLKb
differential input pair. The input signal is then fed to the other CLKa/CLKb input. The VBB should only be used as a
bias for its sink/source capability is limited. When used, the VBB pin should be bypassed to ground via a 0.01μF
Both sides of the differential output must be terminated into 50Ω to ensure that the tight skew specification is
met, even if only one side is used. In most applications all eight differential pairs will be used and therefore
terminated. In the case where fewer than eight pairs are used, all output pairs on the same package side (sharing the
same VCCO) as the pairs being used should be terminated to maintain minimum skew. Failure to do this will result in
small degradations of propagation delay (on the order of 10–20ps) of the outputs being used; while not being
catastrophic to most designs this will result in an increase in skew.
NOTE: Specifications in the ECL/PECL tables are valid when thermal equilibrium is established.
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