AZP94 chip equivalent, clock generation chip.
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* Green and RoHS Compliant / Lead (Pb) Free Package Available 3.0V to 5.5V Operation Selectable Divide Ratio Sel.
D or D ¯ may be connected directly to VBB to form a single 1880Ω bias resistor. The VBB pin supports 1.5mA sink/source .
The AZP94 is a specialized ÷1 or ÷2 clock generation part including an enable/reset function. The divide ratio is selected with the DIV-SEL pin/pad. When DIV-SEL is open (NC), the AZP94 functions as a standard receiver. If DIV-SEL is connected to VEE.
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