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AZP92 - Clock Generation Chip

Description

The AZP92 is a specialized ÷1 or ÷2 clock generation part including an enable/reset function.

The divide ratio is selected with the DIV-SEL pin/pad.

When DIV-SEL is open (NC), the AZP92 functions as a standard receiver.

Features

  • Green and RoHS Compliant / Lead (Pb) Free Package Available 3.0V to 5.5V Operation Selectable Divide Ratio Selectable Enable Polarity and Threshold (CMOS/TTL or PECL) Selectable Input Biasing High Bandwidth for ≥1GHz Available in a MLP 8 (2x2) Package IBIS Model File Available on Arizona Microtek Website.

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Datasheet preview – AZP92

Datasheet Details

Part number AZP92
Manufacturer Arizona Microtek
File Size 132.98 KB
Description Clock Generation Chip
Datasheet download datasheet AZP92 Datasheet
Additional preview pages of the AZP92 datasheet.

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Full PDF Text Transcription

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www.DataSheet4U.com ARIZONA MICROTEK, INC. AZP92 ECL/PECL ÷1, ÷2 Clock Generation Chip with Selectable Enable FEATURES • • • • • • • • Green and RoHS Compliant / Lead (Pb) Free Package Available 3.0V to 5.5V Operation Selectable Divide Ratio Selectable Enable Polarity and Threshold (CMOS/TTL or PECL) Selectable Input Biasing High Bandwidth for ≥1GHz Available in a MLP 8 (2x2) Package IBIS Model File Available on Arizona Microtek Website PACKAGE MLP 8 (2x2) Green / RoHS Compliant / Lead (Pb) Free DIE 1 2 3 4 PACKAGE AVAILABILITY PART NO. AZP92NAG AZP92X MARKING P1G N/A NOTES 1,2 3,4 Add R1 at end of part number for 7 inch (1K parts), R2 for 13 inch (2.5K parts) Tape & Reel. Date code format: “Y” for year followed by “WW” for week.
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