Arizona Microtek AZP94
The AZP94 is a specialized ÷1 or ÷2 clock generation part including an enable/reset function. The divide ratio is selected with the DIV-SEL pin/pad. When DIV-SEL is open (NC), the AZP94 functions as a standard receiver.| Part No. | AZP94 |
|---|---|
| Datasheet | AZP94 Download |
| Manufacturer | Arizona Microtek |
| Description | Clock Generation Chip |
| Buy | Stock & Price |
FEATURES
●●
●
●
●
●
●
●
●
● Green and RoHS Compliant / Lead (Pb) Free Package Available 3.0V to 5.5V Operation Selectable Divide Ratio Selectable Enable Polarity and Threshold (CMOS/TTL or PECL) Tristate Compatible Outputs Input Buffer Powers Down when Disabled Selectable Input Biasing High Bandwidth for ≥1GHz Available in a MLP 8 (2x2) Package IBIS Model File Available on Arizona Microtek Website PACKAGE MLP 8 (2x2) Green / RoHS Compliant / Lead (Pb) Free DIE 1 2 3 4 PACKAGE AVAILABILITY PART NO. AZP94NAG AZP94XP MARKING J4G <Date Code> N/A NOTES 1,2 3,4 Add R1 at end of part number for 7 inch (1K parts), R2 for 13 inch (2.5K parts) Tape & Reel. Date code format: “Y” for year followed by “WW” for week. Waffle Pack, die thickness 180µ. Contact factory for availability.
DESCRIPTION
If DIV-SEL is connected to VEE, it functions as a ÷2 divider. Enable (EN) functionality is selected with the EN-SEL pin/pad which has three valid states: open (NC), VEE, or connected to VEE via a 20kΩ ± 20% resistor.
