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CML

FX465 Datasheet Preview

FX465 Datasheet

Extended Code CTCSS Encoder/Decoder

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CML Semiconductor Products
PRODUCT INFORMATION
FX465 Extended Code CTCSS
Encoder/Decoder
Features
Low-Voltage (3-Volt) Supply
47 Programmable Sub-Audio
Tones + NOTONE
Meets MPT1306 and TIA/EIA 603
High Voiceband/CTCSS Isolation
Separate Sub-Audio and Rx/Tx
Audio Paths and Filtering
Publication D/465/2 May 1996
Applications
Advance Information
Mobile Radio Systems
Community Base Stations
“Sports Radio” (Japan)
Sub-Audio Signalling and
Selective Calling
Status and Alarm Systems
Amateur Radio
TONE IN
TONE IN
FILTER
f TONE
LOAD/LATCH
D5/SERIAL ENABLE
D4/SERIAL ENABLE
D3/SERIAL DATA IN
D2/SERIAL CLOCK
D1
D0
RX/TX
PTL
XTAL/CLOCK
XTAL
CLKS
+
-
DIGITAL
INTERFACE
AND
CLOCK
GENERATION
TONE DECODE
FILTER
CLKS
REFERENCE
VOLTAGE
-
+
CLKS/XTAL
CLKS/XTAL
TONE DETECT
LOGIC
TONE OUT FILTER
Rx TONE DETECT
Tx TONE OUT
A0 - A5
D0 - D10
TONE
ROM
48 x 10
VDD
VSS
VBIAS
FX465
TX AUDIO IN
CLK
Tx AUDIO OUT
RX AUDIO IN
DECODE COMPARATOR REF
DECODE COMPARATOR IN
Fig.1 Functional Block Diagram
AUDIO FILTER
+
-
Brief Description
The FX465 is a 3-volt, half-duplex predictive
Continuous Tone Controlled Squelch System (CTCSS)
encoder/decoder microcircuit. The FX465 has integral
voice-band filtering for prefiltering of Tx audio and the
rejection of the CTCSS tone in receive.
Under µProcessor control, the FX465 will encode
and decode any one of 47 sub-audio frequencies
(+NOTONE) in the range 67.0Hz to 254.1Hz. Tone
frequencies and all functional commands can be
loaded to the device in either pin-selectable 8-bit
parallel or serial format.
A separate, Rx/Tx voice-audio path is available with
a highpass (sub-audio reject) filter automatically placed
in the relevant Rx or Tx voice line.
Rx AUDIO OUT
Rx TONE DECODE
New SSOP D5
package
The Rx sub-audio (CTCSS) path contains a
(selected tone frequency) bandpass filter and period
detector providing a logic level output (Rx Tone Detect)
to indicate a successful decode operation.
Rx “Press to Listen” (PTL) and Tx “Squelch-Tail
Elimination” functions are available in both command
loading modes. The squelch-tail elimination function
will provide (Tx tone) phase-reversal to minimise the
annoying audio outputs that occur at the receiver on
completion of a transmission.
Tone frequencies and filter accuracies are
maintained by an on-chip 4.0MHz clock oscillator
employing an external crystal or clock pulse input.
The FX465, which exhibits high audio and sub-audio
performance with low falsing, is available in a 24-pin
plastic small outline SSOP package.




CML

FX465 Datasheet Preview

FX465 Datasheet

Extended Code CTCSS Encoder/Decoder

No Preview Available !

Pin Number
FX465 D5
1 VDD: Positive supply.
Function
2 Xtal/CIock: Input to the on-chip inverter; used with a 4.0MHz Xtal or external clock source.
3 Xtal: Output of the on-chip inverter (clock output).
4 Load/Latch: Controls 8 on-chip latches and is used to latch Rx/Tx, PTL, D - D . This pin is internally
05
pulled to VDD. A logic ‘1’ applied to this input puts the 8 latches into a 'transparent' mode. A logic ‘0’
applied to this input puts the 8 latches into the ‘latched’ mode.
In parallel mode data is loaded and latched by a logic ‘1’ to ‘0’ transition (see Figure 4).
In serial mode data is loaded and latched by a ‘0’ to ‘1’ to ‘0’ strobe pulse on this pin (see Figure 4).
5
D /Serial Enable: Data input D (Parallel Mode); Serial Enable (Serial Mode).
55
A logic ‘l’ applied to this input, together with a logic ‘0’ applied to D4/Serial Enable, will put the device
into 'Serial Mode' (see Figure 4). This pin is internally pulled to VDD.
6 D4/Serial Enable: Data input D4 (Parallel Mode); Serial Enable (Serial Mode).
A logic ‘0’ applied to this input, together with a logic ‘1’ applied to D5/Serial Enable, will place the device
into ‘Serial Mode’ (see Figure 4). This pin internally pulled to V .
DD
7 D3/Serial Data In: Data input D3 (Parallel Mode); Serial Data Input (Serial Mode).
In Serial Mode this pin becomes the serial data input for D5 - D0, Rx/Tx, PTL (see Figure 4). D5 is
clocked-in first and PTL last. This pin internally pulled to V .
DD
8 D2/Serial Clock: Data input D2 (Parallel Mode); Serial Clock Input (Serial Mode).
In Serial Mode this pin becomes the Serial Clock input. Data is clocked on the positive-going edge (see
Figure 4). This pin is internally pulled to VDD.
9 D1: Data input D1 (Parallel Mode); Not used (Serial Mode). This pin is internally pulled to VDD.
10
D : Data input D (Parallel Mode); Not used (Serial Mode). This pin is internally pulled to V .
00
DD
11 VSS: Negative supply.
12
Decode Comparator
the logical state of the
RRexfT. o(In/Pe):DeInctoedrneaplliyn.bRiaxseTdontoeVDDeD/c3odoer 2=VlDoDg/3ic
via
‘1’
1.0Mresistors depending
will bias this input to 2VDD/3,
on
a
logic ‘0’ will bias this input to VDD/3. This input provides the decode comparator reference voltage;
switching of bias voltages provides hysteresis to reduce 'chatter' under marginal conditions.
2


Part Number FX465
Description Extended Code CTCSS Encoder/Decoder
Maker CML
Total Page 9 Pages
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