28C256 Datasheet | Catalyst

FEATURES s Fast Read Access Times: 120/150ns s Low Power CMOS Dissipation: s Hardware and Software Write Protection s Automatic Page Write Operation: - Active: 25 m A Max. - Standby: 150 µA Max. s Simple Write Operation: - 1 to 64 Bytes in 5ms - Page Load Timer s End of Write Detection: - On-Chip Address and Data Latches - Self-Timed Write Cycle with Auto-Clear s Fast Write Cycle Time: - Toggle Bit - DATA Polling s 100,000 Program/Erase Cycles s 100 Year Data Retention s merical, Industrial and Automotive - 5ms Max s CMOS and TTL patible I/O Temperature Ranges DESCRIPTION The CAT28C256 is a fast, low power, 5V-only CMOS parallel E2PROM organized as 32K x 8-bits. It requires a simple interface for in-system programming. On-chip address and data latches, self-timed write cycle with autoclear and VCC power up/down write protection eliminate additional timing and protection hardware. DATA Polling and Toggle status bits signal the start and end of the selftimed write cycle. Additionally, the CAT28C256 features hardware and software write protection. The CAT28C256 is manufactured using Catalyst’s advanced CMOS floating gate technology. It is designed to endure 100,000 program/erase cycles and has a data retention of 100 years. The device is available in JEDEC approved 28-pin DIP, 28-pin TSOP or 32-pin PLCC packages. BLOCK DIAGRAM A6- A14 ADDR. BUFFER & LATCHES INADVERTENT WRITE PROTECTION ROW DECODER 32,768 x 8 E2PROM ARRAY 64 BYTE PAGE REGISTER HIGH VOLTAGE GENERATOR CE OE WE CONTROL LOGIC I/O BUFFERS TIMER DATA POLLING AND TOGGLE BIT COLUMN DECODER 5096 FHD F02 I/O0- I/O7 A0- A5 ADDR. BUFFER & LATCHES © 1998 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice Doc. No. 25020-0A 2/98 CAT28C256 PIN CONFIGURATION DIP Package (P) A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VCC WE A13 A8 A9 A11 OE A10 CE I/O7 I/O6 I/O5 I/O4 I/O3 PLCC Package (N) A14 NC...