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CAT24C03 - I2C Serial EEPROM

Download the CAT24C03 datasheet PDF. This datasheet also covers the CAT24C05 variant, as both devices belong to the same i2c serial eeprom family and are provided as variant models within a single manufacturer datasheet.

Description

The CAT24C03/CAT24C05 is a 2-kb/4-kb CMOS Serial EEPROM device organized internally as 16/32 pages of 16 bytes each, for a total of 256x8/512x8 bits.

These devices support both Standard (100kHz) as well as Fast (400kHz) I2C protocol.

Features

  • 2-Kb and 4-Kb I2C Serial EEPROM with Partial Array Write Protection DEVICE.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (CAT24C05_CatalystSemiconductor.pdf) that lists specifications for multiple related part numbers.

Datasheet Details

Part number CAT24C03
Manufacturer Catalyst Semiconductor
File Size 459.48 KB
Description I2C Serial EEPROM
Datasheet download datasheet CAT24C03 Datasheet

📁 Similar Datasheet

Part Number Description Manufacturer
CAT24C03 2-Kb and 4-Kb I2C Serial EEPROM ON Semiconductor
CAT24C01 CMOS Serial EEPROM ON Semiconductor
CAT24C02 CMOS Serial EEPROM ON Semiconductor
CAT24C04 CMOS Serial EEPROM ON Semiconductor
CAT24C05 2-Kb and 4-Kb I2C Serial EEPROM ON Semiconductor

Other Datasheets by Catalyst Semiconductor

Part Number Description
CAT24C00 128-Bit Serial EEPROM
CAT24C01 Serial EPROM
CAT24C01B 1K-Bit Serial EEPROM
CAT24C01BPA-1.8TE13 1K-Bit Serial EEPROM
CAT24C02 Serial EPROM

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
CAT24C03/05 FEATURES 2-Kb and 4-Kb I2C Serial EEPROM with Partial Array Write Protection DEVICE DESCRIPTION The CAT24C03/CAT24C05 is a 2-kb/4-kb CMOS Serial EEPROM device organized internally as 16/32 pages of 16 bytes each, for a total of 256x8/512x8 bits. These devices support both Standard (100kHz) as well as Fast (400kHz) I2C protocol. Data is written by providing a starting address, then loading 1 to 16 contiguous bytes into a Page Write Buffer, and then writing all data to non-volatile memory in one internal write cycle. Data is read by providing a starting address and then shifting out data serially while automatically incrementing the internal address count. Write operations can be inhibited for upper half of memory by taking the WP pin High.
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