Figure 3 Single-Ended Input Configuration
Figure 4 Differential Input Configuration
ment. In a single-ended configuration, the input pins should be
connected as shown in Figure 3. Figure 4 shows the necessary
connections for a differential input configuration.
The low and high group tones are separated by applying the
DTMF signal to the inputs of two sixth-order switched capacitor
bandpass filters with bandwidths that correspond to the low and
high group frequencies listed in Table 2. The low group filter in-
corporates notches at 350 and 440 Hz, providing excellent dial
tone rejection. Each filter output is followed by a single-order
switched capacitor filter that smooths the signals prior to limiting.
Limiting is performed by high-gain comparators with hysteresis
to prevent detection of unwanted low-level signals. The com-
parator outputs provide full-rail logic swings at the incoming
DTMF signal frequencies.
A decoder employs digital counting techniques to determine the
frequencies of the incoming tones, and to verify that they corre-
spond to standard DTMF frequencies. A complex averaging al-
gorithm protects against tone simulation by extraneous signals
(such as voice), while tolerating small deviations in frequency.
The algorithm provides an optimum combination of immunity to
talkoff with tolerance to interfering frequencies (third tones) and
noise. When the detector recognizes the presence of two valid
tones (referred to as “signal condition”), the early steering (ESt)
output goes to an active state. Any subsequent loss of signal
condition will cause ESt to assume an inactive state.
Steering Circuit: Before a decoded tone pair is registered, the
receiver checks for a valid signal duration (referred to as “char-
acter recognition condition”). This check is performed by an ex-
ternal RC time constant driven by ESt. A logic high on ESt
Table 1 Pin Functions
D0 - D3
Noninverting op-amp input.
Inverting op-amp input.
Gain select. Gives access to output of front end differential amplifier for connection of feedback resistor.
Reference voltage output. Nominally VDD/2 is used to bias inputs at mid-rail.
Negative power supply input.
DTMF clock/oscillator input.
Clock output. A 3.5795 MHz crystal connected between OSC1 and OSC2 completes the internal oscillator circuit.
Dual tone multifrequency (DTMF) output.
Read/write input. Controls the direction of data transfer to and from the microprocessor and the receiver/transmitter. TTL
Chip select. TTL input (CS = 0 to select the chip).
Register select input. See Table 6. TTL compatible.
System clock input. May be continuous or strobed only during read or write. TTL compatible.
Interrupt request to microprocessor (open-drain output). Also, when call progress (CP) mode has been selected and inter-
rupt enabled, the IRQ/CP pin will output a rectangular wave signal representative of the input signal applied at the input
op-amp. The input signal must be within the bandwidth limits of the call progress filter. See Figure 11
Microprocessor data bus. TTL compatible.
Early steering output. Presents a logic high once the digital algorithm has detected a valid tone pair (signal condition). Any
momentary loss of signal condition will cause ESt to return to a logic low.
Steering input/guard time output (bidirectional). A voltage greater than VTSt detected at St causes the device to register the
detected tone pair and update the output latch. A voltage less than VTSt frees the device to accept a new tone pair. The
GT output acts to reset the external steering time-constant; its state is a funciton of ESt and the voltage on St.
Positive power supply input.
40-406-00012, Rev. G