CY23S08 buffer equivalent, 3.3v zero delay buffer.
* Zero input output propagation delay, adjustable by capacitive load on FBK input
* Multiple configurations (see Available CY23S08 Configurations on page 4)
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The part has an on-chip PLL which locks to an input clock presented on the REF pin. The PLL feedback must be driven int.
The CY23S08 is a 3.3 V zero delay buffer designed to distribute high-speed clocks in PC, workstation, datacom, telecom, and other high-performance applications. The part has an on-chip PLL which locks to an input clock presented on the REF pin. The P.
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