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CY23S09 - Low Cost 3.3V Spread Aware Zero Delay Buffer

General Description

The CY23S09 is a low cost 3.3 V zero delay buffer designed to distribute high speed clocks and is available in a 16-pin SOIC package.

The CY23S05 is an 8-pin version of the CY23S09.

Key Features

  • 10 MHz to 100 MHz and 133 MHz operating range, compatible with CPU and PCI bus frequencies.
  • Zero input-output propagation delay.
  • Multiple low skew outputs.
  • Output-output skew less than 250 ps.
  • Device-device skew less than 700 ps.
  • One input drives five outputs (CY23S05).
  • One input drives nine outputs, grouped as 4 + 4 + 1 (CY23S09).
  • Less than 200 ps Cycle-to-cycle jitter.
  • Test mode to bypass PLL (CY23S09 only, see Select Input Decoding for CY23S09 on.

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📁 Similar Datasheet

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Other Datasheets by Cypress (now Infineon)

Part Number Description
CY23S02 Frequency Multiplier and Zero Delay Buffer
CY23S05 Low Cost 3.3V Spread Aware Zero Delay Buffer
CY23S08 3.3V Zero Delay Buffer
CY2304 3.3V Zero Delay Buffer
CY2304NZ Four Output PCI-X and General Purpose Buffer

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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CY23S09, CY23S05 Low Cost 3.3 V Spread Aware Zero Delay Buffer Features ■ 10 MHz to 100 MHz and 133 MHz operating range, compatible with CPU and PCI bus frequencies ■ Zero input-output propagation delay ■ Multiple low skew outputs ❐ Output-output skew less than 250 ps ❐ Device-device skew less than 700 ps ❐ One input drives five outputs (CY23S05) ❐ One input drives nine outputs, grouped as 4 + 4 + 1 (CY23S09) ■ Less than 200 ps Cycle-to-cycle jitter ■ Test mode to bypass PLL (CY23S09 only, see Select Input Decoding for CY23S09 on page 4) ■ Available in space saving 16-pin, 150-mil SOIC, 4.4 mm TSSOP (CY23S09) or 8-pin, 150-mil SOIC package (CY23S05) ■ 3.3 V operation, advanced 0.65 CMOS technology ■ Spread Aware Functional Description The CY23S09 is a low cost 3.