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CY14B256Q3 - 256-Kbit (32 K X 8) Serial (SPI) nvSRAM

This page provides the datasheet information for the CY14B256Q3, a member of the CY14B256Q1 256-Kbit (32 K X 8) Serial (SPI) nvSRAM family.

Description

9 Status Register 10 Read Status Register (RDSR) Instruction 10 Write Status Register (WRSR) Instruction 10 Write Protection and Block Protection 11 Write Enable (WREN) Instruction 11 Write Disable (WRDI) Instruction 11 Block Protection 11 Write Protect (WP) Pin 12 Memory Access 12 Read Se

Features

  • 256-Kbit nonvolatile static random access memory (nvSRAM).
  • Internally organized as 32 K × 8.
  • STORE to QuantumTrap nonvolatile elements initiated automatically on power-down (AutoStore) or by user using HSB pin (Hardware STORE) or SPI instruction (Software STORE).
  • RECALL to SRAM initiated on power-up (Power-Up RECALL) or by SPI instruction (Software RECALL).
  • Automatic STORE on power-down with a small capacitor (except for CY14B256Q1) High reliability.
  • Infini.

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Datasheet preview – CY14B256Q3

Datasheet Details

Part number CY14B256Q3
Manufacturer Cypress
File Size 1.12 MB
Description 256-Kbit (32 K X 8) Serial (SPI) nvSRAM
Datasheet download datasheet CY14B256Q3 Datasheet
Additional preview pages of the CY14B256Q3 datasheet.

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Full PDF Text Transcription

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CY14B256Q1 CY14B256Q2 CY14B256Q3 256-Kbit (32 K × 8) Serial (SPI) nvSRAM 256-Kbit (32 K × 8) Serial (SPI) nvSRAM Features ■ ■ 256-Kbit nonvolatile static random access memory (nvSRAM) ❐ Internally organized as 32 K × 8 ❐ STORE to QuantumTrap nonvolatile elements initiated automatically on power-down (AutoStore) or by user using HSB pin (Hardware STORE) or SPI instruction (Software STORE) ❐ RECALL to SRAM initiated on power-up (Power-Up RECALL) or by SPI instruction (Software RECALL) ❐ Automatic STORE on power-down with a small capacitor (except for CY14B256Q1) High reliability ❐ Infinite read, write, and RECALL cycles ❐ 1 million STORE cycles to QuantumTrap ❐ Data retention: 20 years High-speed serial peripheral interface (SPI) ❐ 40-MHz clock rate ❐ Supports SPI mode 0 (0,0) and mode 3
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