CY28343 buffer equivalent, zero delay sdr/ddr clock buffer.
* Phase-lock loop clock distribution for DDR and SDR SDRAM applications
* One-single-end clock input to 6 pairs DDR outputs or 13 SDR outputs.
* External feed.
* One-single-end clock input to 6 pairs DDR outputs or 13 SDR outputs.
* External feedback pins FBIN_SDR/FBOUT_S.
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