CY2DP818 buffer equivalent, 1:8 clock fanout buffer.
* Low-voltage operation VDD = 3.3 V
* 1:8 fanout
* Operation to350 MHz
* Single input configurable for LVDS, LVPECL, or LVTTL
* 8 pair of LVPECL outp.
the large fanout from a single input reduces loading on the input clock. The CY2DP818 is ideal for both level translati.
The Cypress CY2DP818 fanout buffer features a single LVDS or a single ended LVTTL compatible input and eight LVPECL output pairs. Designed for data-communications clock management applications, the large fanout from a single input reduces loading on .
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