CY2SSTV16859 Datasheet, Cypress Semiconductor

* Differential clock inputs up to 280 MHz
* Supports LVTTL switching levels on the RESET# pin
* Output drivers have controlled edge rates, so no external resi.

This 13-bit to 26-bit registered buffer is designed for 2.3V to 2.7 VDD operations. All inputs are compatible with the JEDEC Standard for SSTL-2, except the LVCMOS reset (RESET#) input. All outputs are SSTL_2, Class II compatible. Block Diagram Pin.

CY2SSTV16857

CY2SSTV850

CY2SSTV855

CY2SSTV857-27

CY2SSTV857-32

CY2SSTV8575

CY2SSTU877

CY2037

CY2071A

CY2077

CY2081

CY20AAJ-8F

CY20AAJ-8H