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CY2SSTV16859 - 13-Bit to 26-Bit Registered Buffer PC2700-/PC3200-Compliant

General Description

This 13-bit to 26-bit registered buffer is designed for 2.3V to 2.7 VDD operations.

All inputs are compatible with the JEDEC Standard for SSTL-2, except the LVCMOS reset (RESET#) input.

All outputs are SSTL_2, Class II compatible.

Key Features

  • Differential clock inputs up to 280 MHz.
  • Supports LVTTL switching levels on the RESET# pin.
  • Output drivers have controlled edge rates, so no external resistors are required.
  • Two KV ESD protection.
  • Latch-up performance exceeds 100 mA per JESD78, Class II.
  • 64-pin TSSOP/JEDEC and 56-pin QFN package availability.
  • JEDEC specification supported The CY2SSTV16859 operates from a differential clock (CLK and CLK#) of frequency up to 280 MHz.

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Full PDF Text Transcription for CY2SSTV16859 (Reference)

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www.DataSheet4U.com CY2SSTV16859 13-Bit to 26-Bit Registered Buffer PC2700-/PC3200-Compliant Features • Differential clock inputs up to 280 MHz • Supports LVTTL switching...

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s • Differential clock inputs up to 280 MHz • Supports LVTTL switching levels on the RESET# pin • Output drivers have controlled edge rates, so no external resistors are required. • Two KV ESD protection • Latch-up performance exceeds 100 mA per JESD78, Class II • 64-pin TSSOP/JEDEC and 56-pin QFN package availability • JEDEC specification supported The CY2SSTV16859 operates from a differential clock (CLK and CLK#) of frequency up to 280 MHz. Data are registered at crossing of CLK going high and CLK# going low. When RESET# is low, the differential input receivers are disabled, and undriven (floating) data and clock inputs

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