CY2SSTV16859 Datasheet PDF - SpectraLinear 13-Bit to 26-Bit Registered Buffer Specs

CY2SSTV16859 - 13-Bit to 26-Bit Registered Buffer

Datasheet Summary

Description

This 13-bit to 26-bit registered buffer is designed for 2.3V to 2.7 VDD operations.

All inputs are compatible with the JEDEC Standard for SSTL-2, except the LVCMOS reset (RESET#) input.

All outputs are SSTL_2, Class II compatible.

Features

Differential clock inputs up to 280 MHz.
Supports LVTTL switching levels on the RESET# pin.
Output drivers have controlled edge rates, so no external resistors are required. www. DataSheet4U. com The CY2SSTV16859 operates from a differential clock (CLK and CLK#) of frequency up to 280 MHz. Data are registered at crossing of CLK going high and CLK# going low. When RESET# is low, the differential input receivers are disabled, and undriven (floating) data and clock inputs.

Datasheet Details

Part number	CY2SSTV16859
Manufacturer	SpectraLinear
File Size	170.22 KB
Description	13-Bit to 26-Bit Registered Buffer
Datasheet	CY2SSTV16859 Datasheet
Additional preview pages of the CY2SSTV16859 datasheet.

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Full PDF Text Transcription

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CY2SSTV16859 13-Bit to 26-Bit Registered Buffer PC2700-/PC3200-Compliant Features • Differential clock inputs up to 280 MHz • Supports LVTTL switching levels on the RESET# pin • Output drivers have controlled edge rates, so no external resistors are required. www.DataSheet4U.com The CY2SSTV16859 operates from a differential clock (CLK and CLK#) of frequency up to 280 MHz. Data are registered at crossing of CLK going high and CLK# going low. When RESET# is low, the differential input receivers are disabled, and undriven (floating) data and clock inputs are allowed. The LVCMOS RESET# input must always be held at a valid logic high or low level. To ensure defined outputs from the register before a stable clock has been supplied, RESET# must be held in the low state during power up.

Published: Nov 18, 2008 |