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CY2SSTV850 Datasheet Differential Clock Buffer/Driver

Manufacturer: Cypress (now Infineon)

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General Description

This PLL clock buffer is designed for 2.5 VDD and 2.5 AVDD operation and differential data input and output levels.

This device is a zero-delay buffer that distributes a differential clock input pair (CLKINT, CLKINC) to ten differential pair of clock outputs (YT[0:9], YC[0:9]) and one differential pair feedback clock output (FBOUTT, FBOUTC).

The clock outputs are individually controlled by the serial inputs SCLK and SDATA.

Overview

STV850 CY2SSTV850 Differential Clock Buffer/Driver.

Key Features

  • Phase-locked loop clock distribution for Double Data Rate Synchronous DRAM.

📁 Similar Datasheet

Brand Logo Part Number Description Manufacturer
Silicon Laboratories Logo CY2SSTV850 Differential Clock Buffer/Driver Silicon Laboratories

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