CY7B994V Datasheet | Cypress

Features - 12/100-MHz (CY7B993V), or 24/185-MHz (CY7B994V) output operation - Matched pair outputs skew <200 ps - Zero input-to-output delay - 18 LVTTL 50% duty-cycle outputs capable of driving 50Ω terminated lines - mercial Temp. Range with 16 outputs at 185 MHz - Industrial Temp. Range with 6 outputs at 185 MHz - 3.3V LVTTL/LV Differential (LVPECL), Fault Tolerant and Hot Insertable reference inputs - Phase adjustments in 625/1300 ps steps up to ±10.4 ns - Multiply/Divide ratios of (1- 6, 8, 10, 12):(1- 6, 8, 10, 12) - Operation up to 12x input frequency - Individual Output Bank disable for aggressive power management and EMI reduction - Output high-impedance option for testing purposes - Fully integrated PLL with Lock Indicator - Low Cycle-to-Cycle Jitter (<100 ps peak-peak) - Single 3.3V ± 10% supply - 100-Pin TQFP package Functional Description The CY7B993V and CY7B994V High-Speed Multi-Phase PLL Clock Buffers offer user-selectable control over system clock functions. This multiple-output clock driver provides the system integrator with functions necessary to optimize the timing of high-performance puter and munication systems. Eighteen configurable outputs can each drive terminated transmission lines with impedances as low as 50Ω while delivering minimal and specified output skews at LVTTL levels. The outputs are arranged in five banks. Banks 1 to 4 of four outputs allow a divide function of 1 to 12, while simultaneously allowing phase adjustments in 625 ps- 1300 ps increments up to 10.4 ns. One of the output banks also includes an independent clock invert function. The feedback bank consists of two outputs, which allows divide-by functionality from 1 to 12 and limited phase adjustments. Any one of these eighteen outputs can be connected to the feedback input as well as driving other inputs. Selectable reference input is a fault tolerance feature which allows smooth change over to secondary clock source, when the primary clock source is not in operation. The...