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Cypress Semiconductor Electronic Components Datasheet

CY7C0430BV Datasheet

10 Gb/s 3.3V QuadPort DSE

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CY7C0430BV
CY7C0430CV
10 Gb/s 3.3V QuadPort™ DSE Family
Features
• QuadPort™ datapath switching element (DSE) family
allows four independent ports of access for data path
management and switching
• High-bandwidth data throughput up to 10 Gb/s
• 133-MHz[1] port speed x 18-bit-wide interface × 4 ports
• High-speed clock to data access 4.2 ns (max.)
• Synchronous pipelined device
— 1-Mb (64K × 18) switch array
• 0.25-micron CMOS for optimum speed/power
• IEEE 1149.1 JTAG boundary scan
• Width and depth expansion capabilities
• BIST (Built-In Self-Test) controller
QuadPort DSE Family Applications
• Dual Chip Enables on all ports for easy depth expansion
• Separate upper-byte and lower-byte controls on all
ports
• Simple array partitioning
— Internal mask register controls counter wrap-around
— Counter-Interrupt flags to indicate wrap-around
— Counter and mask registers readback on address
• 272-ball BGA package (27-mm × 27-mm × 1.27-mm ball
pitch)
• Commercial and industrial temperature ranges
• 3.3V low operating power
— Active = 750 mA (maximum)
— Standby = 15 mA (maximum
PORT 1
PORT 3
PORT 2
BUFFERED SWITCH
PORT 4
PORT 2
PORT 1
PORT 3
PORT 4
REDUNDANT DATA MIRROR
Note:
1. fMAX2 for commercial is 135 MHz and for industrial is 133 MHz.
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document #: 38-06027 Rev. *B
Revised May 23, 2006


Cypress Semiconductor Electronic Components Datasheet

CY7C0430BV Datasheet

10 Gb/s 3.3V QuadPort DSE

No Preview Available !

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PORT 1
PORT 2
PORT 4
PORT 3
DATA PATH AGGREGATOR
Processor 1
CY7C0430BV
CY7C0430CV
Pre-processed DATA Path
QuadPort
DSE Family
Processed DATA Path
Processor 2
DATA PATH MANAGER FOR
PARALLEL PACKET PROCESSING
PORT 1
PORT 2
Queue #1
Queue #2
PORT 3
PORT 4
DATA CLASSIFICATION ENGINE
Functional Description
The Quadport Datapath Switching Element (DSE) family offers
four ports that may be clocked at independent frequencies
from one another. Each port can read or write up to 133 MHz[1],
giving the device up to 10 Gb/s of data throughput. The device
is 1-Mb (64K × 18) in density. Simultaneous reads are allowed
for accesses to the same address location; however, simulta-
neous reading and writing to the same address is not allowed.
Any port can write to a certain location while other ports are
reading that location simultaneously, if the timing spec for port
to port delay (tCCS) is met. The result of writing to the same
location by more than one port at the same time is undefined.
Data is registered for decreased cycle time. Clock to data valid
tCD2 = 4.2 ns. Each port contains a burst counter on the input
address register. After externally loading the counter with the
initial address the counter will self-increment the address inter-
nally (more details to follow). The internal write pulse width is
independent of the duration of the R/W input signal. The
internal write pulse is self-timed to allow the shortest possible
cycle times.
A HIGH on CE0 or LOW on CE1 for one clock cycle will power
down the internal circuitry to reduce the static power
consumption. One cycle is required with chip enables asserted
to reactivate the outputs.
The CY7C0430BV and CY7C0430CV (64K × 18 device)
supports burst contains for simple array partitioning. Counter
enable inputs are provided to stall the operation of the address
input and utilize the internal address generated by the internal
counter for fast interleaved memory applications. A port’s burst
Document #: 38-06027 Rev. *B
Page 2 of 37


Part Number CY7C0430BV
Description 10 Gb/s 3.3V QuadPort DSE
Maker Cypress Semiconductor
Total Page 30 Pages
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