CY7C09189V Overview
Two ports are provided, permitting independent, simultaneous access for reads and writes to any location in memory.[4] Registers on control, address, and data lines allow for minimal set-up and hold times. In pipelined output mode, data is registered for decreased cycle time. Clock to data valid tCD2 = 6.5 ns[1] (pipelined).
CY7C09189V Key Features
- True Dual-Ported memory cells which allow simultaneous access of the same memory location
- 6 Flow-Through/Pipelined devices
- 32K x 8/9 organizations (CY7C09079V/179V)
- 64K x 8/9 organizations (CY7C09089V/189V)
- 128K x 8/9 organizations (CY7C09099V/199V)
- 3 Modes
- Flow-Through
- Pipelined
- Pipelined output mode on both ports allows fast 100-MHz operation
- 0.35-micron CMOS for optimum speed/power