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CY7C09359AV - 3.3 V 4 K/8 K x 18 Synchronous Dual Port Static RAM

Download the CY7C09359AV datasheet PDF (CY7C09349AV included). The manufacturer datasheet provides complete specifications, pinout details, electrical characteristics, and typical applications for 3.3 v 4 k/8 k x 18 synchronous dual port static ram.

Features

  • True dual ported memory cells which allow simultaneous access of the same memory location.
  • Two flow-through/pipelined devices.
  • 4 K × 18 organization (CY7C09349AV).
  • 8 K × 18 organization (CY7C09359AV).
  • Three modes.
  • Flow-through.
  • Pipelined.
  • Burst.
  • Pipelined output mode on both ports allows fast 67-MHz operation.
  • 0.35-micron complementary metal oxide semiconductor (CMOS) for optimum speed/power Logic Block Diagram R/WL UBL.
  • High-speed clock t.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (CY7C09349AV-CypressSemiconductor.pdf) that lists specifications for multiple related part numbers.

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Other Datasheets by Cypress Semiconductor
  • CY7C09349AV - 3.3 V 4 K/8 K x 18 Synchronous Dual Port Static RAM
  • CY7C09369V - 3.3 V 16K / 32K / 64K x 16 / 18 Synchronous Dual-Port Static RAM
  • CY7C09379 - 32K/64K X 16/18 Synchronous Dual Port Static RAM
  • CY7C09389 - 32K/64K X 16/18 Synchronous Dual Port Static RAM
  • CY7C09389V - 3.3 V 16K / 32K / 64K x 16 / 18 Synchronous Dual-Port Static RAM
  • CY7C09079V - (CY7C09xx9V) 3.3V 32K/64K/128K x 8/9 Synchronous Dual-Port Static RAM
  • CY7C09089 - (CY7C09xx9) 64K/128K x 8/9 Synchronous Dual-Port Static RAM
  • CY7C09089V - (CY7C09xx9V) 3.3V 32K/64K/128K x 8/9 Synchronous Dual-Port Static RAM

Full PDF Text Transcription

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CY7C09359AV3.3 V 4 K/8 K × 18 Synchronous Dual Port Static RAM CY7C09349AV CY7C09359AV 3.3 V 4 K/8 K × 18 Synchronous Dual Port Static RAM 3.3 V 4 K/8 K × 18 Synchronous Dual Port Static RAM Features ■ True dual ported memory cells which allow simultaneous access of the same memory location ■ Two flow-through/pipelined devices ❐ 4 K × 18 organization (CY7C09349AV) ❐ 8 K × 18 organization (CY7C09359AV) ■ Three modes ❐ Flow-through ❐ Pipelined ❐ Burst ■ Pipelined output mode on both ports allows fast 67-MHz operation ■ 0.35-micron complementary metal oxide semiconductor (CMOS) for optimum speed/power Logic Block Diagram R/WL UBL ■ High-speed clock to data access 9 and 12 ns (max) ■ 3.
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