CY7C1022 Datasheet | Cypress

022CY7C10 .. PRELIMINARY 32K x 16 Static RAM Features - 5.0V operation (± 10%) - High speed - t AA = 12 ns - Low active power - 825 m W (max., 10 ns, “L” version) - Very Low standby power - 500 µW (max., “L” version) - Automatic power-down when deselected - Independent Control of Upper and Lower bytes - Available in 400-mil SOJ enable (BLE) is LOW, then data from I/O pins (I/O1 through I/O8), is written into the location specified on the address pins (A0 through A14). If byte high enable (BHE) is LOW, then data from I/O pins (I/O9 through I/O16) is written into the location specified on the address pins (A0 through A14). Reading from the device is acplished by taking chip enable (CE) HIGH and output enable (OE) LOW while forcing the write enable (WE) HIGH. If byte low enable (BLE) is LOW, then data from the memory location specified by the address pins will appear on I/O1 to I/O8. If byte high enable (BHE) is LOW, then data from memory will appear on I/O9 to I/O16. See the truth table at the back of this data sheet for a plete description of read and write modes. The input/output pins (I/O1 through I/O16) are placed in a high-impedance state when the device is deselected (CE LOW), the outputs are disabled (OE HIGH), the BHE and BLE are disabled (BHE, BLE HIGH), or during a write operation (CE HIGH, and WE LOW). The CY7C1022 is available in standard 400-mil-wide SOJ packages. Functional Description The CY7C1022 is a high-performance CMOS static RAM organized as 32,768 words by 16 bits. This device has an automatic power-down feature that significantly reduces power consumption when deselected. Writing to the device is acplished by taking chip enable (CE) input HIGH and write enable (WE) input LOW. If byte low Logic Block Diagram DATA IN DRIVERS Pin Configuration SOJ Top View NC A 14 A 13 A 12 A11 CE I/O1 I/O2 I/O3 I/O4 VCC VSS I/O5 I/O6 I/O7 I/O8 WE A10 A9 A8 A7 NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44...