CY7C1176V18 Datasheet | Cypress

CY7C1161V18 CY7C1176V18 CY7C1163V18 CY7C1165V18 18-Mbit QDR™-II+ SRAM 4-Word Burst Architecture (2.5 Cycle Read Latency) Features - Functional Description The CY7C1161V18, CY7C1176V18, CY7C1163V18, and CY7C1165V18 are 1.8V Synchronous Pipelined SRAMs equipped with QDR™-II+ architecture. QDR-II+ architecture consists of two separate ports to access the memory array. The read port has dedicated data outputs to support read operations and the write port has dedicated data inputs to support write operations. QDR-II+ architecture has separate data inputs and data outputs to pletely eliminate the need to turn around the data bus that is required with mon IO devices. Each port can be accessed through a mon address bus. Addresses for read and write addresses are latched onto alternate rising edges of the input (K) clock. Accesses to the QDR-II+ read and write ports are pletely independent of one another. In order to maximize data throughput, both read and write ports are equipped with Double Data Rate (DDR) interfaces. Each address location is associated with four 8-bit words (CY7C1161V18), 9-bit words (CY7C1176V18), 18-bit words (CY7C1163V18), or 36-bit words (CY7C1165V18) that burst sequentially into or out of the device. Because data can be transferred into and out of the device on every rising edge of both input clocks K and K, memory bandwidth is maximized while simplifying system design by eliminating bus turnarounds. Depth expansion is acplished with port selects for each port. Port selects allow each port to operate independently. All synchronous inputs pass through input registers controlled by the K or K input clocks. All data outputs pass through output registers controlled by the or K or K input clocks. Writes are conducted with on-chip synchronous self-timed write circuitry. Separate independent read and write data ports - Supports concurrent transactions 300 MHz to 400 MHz clock for high bandwidth 4-word burst to reduce address bus...