CY7C1223F Datasheet 2-Mb (128K x 18) Pipelined DCD Sync SRAM

Manufacturer: Cypress (now Infineon)

CY7C1223F 2-mb (128k x 18) pipelined dcd sync sram by Cypress (now Infineon) - Datasheet Preview

Datasheet Details

Part number	CY7C1223F
Manufacturer	Cypress (now Infineon)
File Size	493.46 KB
Description	2-Mb (128K x 18) Pipelined DCD Sync SRAM
Download	CY7C1223F Download (PDF)

General Description

[1] The CY7C1223F SRAM integrates 131,072 x 18 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation.

All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK).

The synchronous inputs include all addresses, all data inputs, address-pipelining Chip Enable (CE1), depth-expansion Chip Enables (CE2 and CE3), Burst Control inputs (ADSC, ADSP, and ADV), Write Enables (BW[A:B] and BWE), and Global Write (GW).

Overview

www.DataSheet4U.com CY7C1223F 2-Mb (128K x 18) Pipelined DCD Sync.

Key Features

Registered inputs and outputs for pipelined operation.
Optimal for performance (Double-Cycle deselect).
Depth expansion without wait state.
128K × 18-bit common I/O architecture.
3.3V.
5% and +10% core power supply (VDD).
3.3V I/O supply (VDDQ).
Fast clock-to-output time.
3.5 ns (for 166-MHz device).
4.0 ns (for 133-MHz device).
Provide high-performance 3-1-1-1 access rate.
User-selectable.

More Datasheets from Cypress (now Infineon)

Part Number	Description
CY7C122	256 x 4 Static R/W RAM
CY7C1212F	1-Mbit (64K x 18) Pipelined Sync SRAM
CY7C1212H	1-Mbit (64K x 18) Pipelined Sync SRAM
CY7C1214F	1-Mb (32K x 32) Flow-Through Sync SRAM
CY7C1214H	1-Mbit (32K x 32) Flow-Through Sync SRAM
CY7C1215F	1-Mb (32K x 32) Pipelined Sync SRAM
CY7C1215H	1-Mbit (32K x 32) Pipelined Sync SRAM
CY7C1217F	1-Mbit (32K x 36) Flow-Through Sync SRAM
CY7C1217H	1-Mbit (32K x 36) Flow-Through Sync SRAM
CY7C1218F	1-Mb (32K x36) Pipelined Sync SRAM