CY7C1212F - 1-Mbit (64K x 18) Pipelined Sync SRAM

Product Overview

Cypress Semiconductor

Datasheet Details

Part number	CY7C1212F
Manufacturer	Cypress Semiconductor
File Size	359.67 KB
Description	1-Mbit (64K x 18) Pipelined Sync SRAM
Datasheet	CY7C1212F Datasheet
Additional preview pages of the CY7C1212F datasheet.

Product details

Description

The CY7C1212F SRAM integrates 65,536 x 18 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation.

All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK).

Features

Registered inputs and outputs for pipelined operation.
64K × 18 common I/O architecture.
3.3V core power supply.
3.3V I/O operation.
Fast clock-to-output times.
3.5 ns (for 166-MHz device).
4.0 ns (for 133-MHz device).
Provide high-performance 3-1-1-1 access rate.
User-selectable burst counter supporting Intel Pentium® interleaved or linear burst sequences.
Separate processor and controller address strobe.

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Other Datasheets by Cypress Semiconductor

CY7C1212H - 1-Mbit (64K x 18) Pipelined Sync SRAM
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Published: Mar 18, 2009 |