CY7C1219H
Features
- Registered inputs and outputs for pipelined operation
- Optimal for performance (Double-Cycle deselect)
- Depth expansion without wait state
- 32K × 36-bit mon I/O architecture
- 3.3V core power supply (VDD)
- 2.5V/3.3V I/O power supply (VDDQ)
- Fast clock-to-output times
- 3.5 ns (for 166-MHz device)
- Provide high-performance 3-1-1-1 access rate
- User-selectable burst counter supporting Intel® Pentium® interleaved or linear burst sequences
- Separate processor and controller address strobes
- Synchronous self-timed write
- Asynchronous Output Enable
- Available in JEDEC-standard lead-free 100-Pin TQFP package
- “ZZ” Sleep Mode option
Functional Description
[1]
The CY7C1219H SRAM integrates 32K x 36 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). The synchronous inputs include all addresses, all data inputs,...
