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CY7C1214H - 1-Mbit (32K x 32) Flow-Through Sync SRAM

General Description

The CY7C1214H is a 32K x 32 synchronous cache RAM designed to interface with high-speed microprocessors with minimum glue logic.

Maximum access delay from clock rise is 6.5 ns (133-MHz version).

Key Features

  • 32K X 32 common I/O.
  • 3.3V core power supply (VDD).
  • 2.5V/3.3V I/O power supply (VDDQ).
  • Fast clock-to-output times.
  • 6.5 ns (for 133-MHz version).
  • Provide high-performance 2-1-1-1 access rate.
  • User-selectable burst counter supporting Intel® Pentium® interleaved or linear burst sequences.
  • Separate processor and controller address strobes.
  • Synchronous self-timed write.
  • Asynchronous output enable.
  • Avail.

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Other Datasheets by Cypress (now Infineon)

Part Number Description
CY7C1214F 1-Mb (32K x 32) Flow-Through Sync SRAM
CY7C1212F 1-Mbit (64K x 18) Pipelined Sync SRAM
CY7C1212H 1-Mbit (64K x 18) Pipelined Sync SRAM
CY7C1215F 1-Mb (32K x 32) Pipelined Sync SRAM
CY7C1215H 1-Mbit (32K x 32) Pipelined Sync SRAM

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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CY7C1214H www.DataSheet4U.com 1-Mbit (32K x 32) Flow-Through Sync SRAM Features • 32K X 32 common I/O • 3.3V core power supply (VDD) • 2.5V/3.3V I/O power supply (VDDQ) • Fast clock-to-output times — 6.5 ns (for 133-MHz version) • Provide high-performance 2-1-1-1 access rate • User-selectable burst counter supporting Intel® Pentium® interleaved or linear burst sequences • Separate processor and controller address strobes • Synchronous self-timed write • Asynchronous output enable • Available in JEDEC-standard lead-free 100-Pin TQFP package • “ZZ” Sleep Mode option Functional Description[1] The CY7C1214H is a 32K x 32 synchronous cache RAM designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133-MHz version).