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CY7C1215F - 1-Mb (32K x 32) Pipelined Sync SRAM

General Description

and Truth Table for further details).

Write cycles can be one to four bytes wide as controlled by the Byte Write control inputs.

GW when active LOW causes all bytes to be written.

Key Features

  • Registered inputs and outputs for pipelined operation.
  • 32K × 32 common I/O architecture.
  • 3.3V core power supply.
  • 3.3V I/O operation.
  • Fast clock-to-output times.
  • 3.5ns (for 166-MHz device).
  • 4.0 ns (for 133-MHz device).
  • Provide high-performance 3-1-1-1 access rate.
  • User-selectable burst counter supporting Intel Pentium® interleaved or linear burst sequences.
  • Separate processor and controller address strobes.

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Other Datasheets by Cypress (now Infineon)

Part Number Description
CY7C1215H 1-Mbit (32K x 32) Pipelined Sync SRAM
CY7C1212F 1-Mbit (64K x 18) Pipelined Sync SRAM
CY7C1212H 1-Mbit (64K x 18) Pipelined Sync SRAM
CY7C1214F 1-Mb (32K x 32) Flow-Through Sync SRAM
CY7C1214H 1-Mbit (32K x 32) Flow-Through Sync SRAM

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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CY7C1215F www.DataSheet4U.com 1-Mb (32K x 32) Pipelined Sync SRAM Features • Registered inputs and outputs for pipelined operation • 32K × 32 common I/O architecture • 3.3V core power supply • 3.3V I/O operation • Fast clock-to-output times — 3.5ns (for 166-MHz device) — 4.0 ns (for 133-MHz device) • Provide high-performance 3-1-1-1 access rate • User-selectable burst counter supporting Intel Pentium® interleaved or linear burst sequences • Separate processor and controller address strobes • Synchronous self-timed writes • Asynchronous output enable • Offered in JEDEC-standard 100-pin TQFP package • “ZZ” Sleep Mode Option counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK).