CY7C1215F Description
For best-practices remendations, please refer to the Cypress application note System Design Guidelines on .cypress.. Cypress Semiconductor Corporation Document #: 3901 North First Street San Jose, CA 95134 408-943-2600 Revised January 26, 2004 CY7C1215F Selection Guide.
CY7C1215F Key Features
- Registered inputs and outputs for pipelined operation
- 32K × 32 mon I/O architecture
- 3.3V core power supply
- 3.3V I/O operation
- Fast clock-to-output times
- 3.5ns (for 166-MHz device)
- 4.0 ns (for 133-MHz device)
- Provide high-performance 3-1-1-1 access rate
- User-selectable burst counter supporting Intel Pentium® interleaved or linear burst sequences
- Separate processor and controller address strobes