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Cypress Semiconductor Electronic Components Datasheet

CY7C1356CV25 Datasheet

9-Mbit (256K x 36/512K x 18) Pipelined SRAM

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CY7C1354CV25
CY7C1356CV25
9-Mbit (256K × 36/512K × 18)
Pipelined SRAM with NoBL™ Architecture
9-Mbit (256K × 36/512K × 18) Pipelined SRAM with NoBL™ Architecture
Features
Pin-compatible with and functionally equivalent to ZBT™
Supports 250-MHz bus operations with zero wait states
Available speed grades are 250, 200, and 166 MHz
Internally self-timed output buffer control to eliminate the need
to use asynchronous OE
Fully registered (inputs and outputs) for pipelined operation
Byte write capability
Single 2.5 V power supply (VDD)
Fast clock-to-output times
2.8 ns (for 250-MHz device)
Clock enable (CEN) pin to suspend operation
Synchronous self-timed writes
Available in Pb-free 100-pin TQFP package, Pb-free and
non Pb-free 119-ball BGA package and 165-ball FBGA
package
IEEE 1149.1 JTAG-compatible boundary scan
Burst capability–linear or interleaved burst order
“ZZ” sleep mode option and stop clock option
Functional Description
The CY7C1354CV25/CY7C1356CV25[1] are 2.5 V,
256K × 36/512K × 18 synchronous pipelined burst SRAMs with
No Bus Latency™ (NoBL logic, respectively. They are
designed to support unlimited true back-to-back read/write
operations with no wait states. The
CY7C1354CV25/CY7C1356CV25 are equipped with the
advanced (NoBL) logic required to enable consecutive
read/write operations with data being transferred on every clock
cycle. This feature dramatically improves the throughput of data
in systems that require frequent write/read transitions. The
CY7C1354CV25/CY7C1356CV25 are pin-compatible with and
functionally equivalent to ZBT devices.
All synchronous inputs pass through input registers controlled by
the rising edge of the clock. All data outputs pass through output
registers controlled by the rising edge of the clock. The clock
input is qualified by the clock enable (CEN) signal, which when
deasserted suspends operation and extends the previous clock
cycle.
Write operations are controlled by the byte write selects
(BWa–BWd for CY7C1354CV25 and BWa–BWb for
CY7C1356CV25) and a write enable (WE) input. All writes are
conducted with on-chip synchronous self-timed write circuitry.
Three synchronous chip enables (CE1, CE2, CE3) and an
asynchronous output enable (OE) provide for easy bank
selection and output tri-state control. In order to avoid bus
contention, the output drivers are synchronously tri-stated during
the data portion of a write sequence.
For a complete list of related documentation, click here.
Selection Guide
Maximum access time
Maximum operating current
Maximum CMOS standby current
Description
250 MHz
2.8
250
40
200 MHz
3.2
220
40
166 MHz
3.5
180
40
Unit
ns
mA
mA
Note
1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 38-05537 Rev. *Q
• San Jose, CA 95134-1709 • 408-943-2600
Revised November 4, 2016


Cypress Semiconductor Electronic Components Datasheet

CY7C1356CV25 Datasheet

9-Mbit (256K x 36/512K x 18) Pipelined SRAM

No Preview Available !

CY7C1354CV25
CY7C1356CV25
Logic Block Diagram – CY7C1354CV25
A0, A1, A
MODE
CLK C
CEN
ADV/LD
BWa
BWb
BWc
BWd
WE
ADDRESS
REGISTER 0
WRITE ADDRESS
REGISTER 1
A1 D1
Q1 A1'
A0 D0 BURST Q0 A0'
LOGIC
ADV/LD
C
WRITE ADDRESS
REGISTER 2
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
WRITE
DRIVERS
MEMORY
ARRAY
S
E
N
S
E
A
M
P
S
O
U
T
P
U
T
R
E
G
I
S
T
E
R
S
E
D
A
T
A
S
T
E
E
R
I
N
O
U
T
P
U
T
B
U
F
F
E
R
S
E
G
INPUT
REGISTER 1 E
INPUT
REGISTER 0 E
DQs
DQPa
DQPb
DQPc
DQPd
OE
CE1 READ LOGIC
CE2
CE3
ZZ SLEEP
CONTROL
Document Number: 38-05537 Rev. *Q
Page 2 of 35


Part Number CY7C1356CV25
Description 9-Mbit (256K x 36/512K x 18) Pipelined SRAM
Maker Cypress Semiconductor
Total Page 30 Pages
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