CY7C1361C, CY7C1363C - (CY7C1361C / CY7C1363C) 9-Mbit (256K x 36/512K x 18) Flow-Through SRAM

Cypress Semiconductor

The CY7C1361C by Cypress Semiconductor is a (CY7C1361C / CY7C1363C) 9-Mbit (256K x 36/512K x 18) Flow-Through SRAM. Below is the official datasheet preview.

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CY7C1361C (CY7C1361C / CY7C1363C) 9-Mbit (256K x 36/512K x 18) Flow-Through SRAM by Cypress Semiconductor - Datasheet Preview — Official preview page of the **CY7C1361C** (CY7C1361C / CY7C1363C) 9-Mbit (256K x 36/512K x 18) Flow-Through SRAM datasheet (Cypress Semiconductor).

Datasheet Details

Part number	CY7C1361C, CY7C1363C
Manufacturer	Cypress Semiconductor
File Size	531.24 KB
Description	(CY7C1361C / CY7C1363C) 9-Mbit (256K x 36/512K x 18) Flow-Through SRAM
Datasheet	CY7C1363C_CypressSemiconductor.pdf
Note	This datasheet PDF includes multiple part numbers: CY7C1361C, CY7C1363C. Please refer to the document for exact specifications by model.
Additional preview pages of the CY7C1361C datasheet.

CY7C1361C Product details

Description

1] The CY7C1361C/CY7C1363C is a 3.3V, 256K x 36 and 512K x 18 Synchronous Flowthrough SRAMs, respectively designed to interface with high-speed microprocessors with minimum glue logic.Maximum access delay from clock rise is 6.5 ns (133-MHz version).A 2-bit on-chip counter captures the first address in a burst and increments the address automatically for the rest of the burst access.All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK).The syn

Features

Supports 133-MHz bus operations.
256K × 36/512K × 18 common I/O.
3.3V.
5% and +10% core power supply (VDD).
2.5V or 3.3V I/O supply (VDDQ).
Fast clock-to-output times.
6.5 ns (133-MHz version).
7.5 ns (117-MHz version).
8.5 ns (100-MHz version).
Provide high-performance 2-1-1-1 access rate.
User-selectable burst counter supporting Intel Pentium interleaved or linear burst sequences.
Sepa.

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Published: Feb 3, 2010 |