CY7C1363C Datasheet | Cypress

PRELIMINARY CY7C1361C CY7C1363C 9-Mbit (256K x 36/512K x 18) Flow-Through SRAM Features - Supports 133-MHz bus operations - 256K × 36/512K × 18 mon I/O - 3.3V - 5% and +10% core power supply (VDD) - 2.5V or 3.3V I/O supply (VDDQ) - Fast clock-to-output times - 6.5 ns (133-MHz version) - 7.5 ns (117-MHz version) - 8.5 ns (100-MHz version) - Provide high-performance 2-1-1-1 access rate - User-selectable burst counter supporting Intel Pentium interleaved or linear burst sequences - Separate processor and controller address strobes - Synchronous self-timed write - Asynchronous output enable - Available in Lead-Free 100 TQFP,119 BGA and 165 f BGA packages Both 2 and 3 Chip Enable Options for TQFP - IEEE 1149.1 patible JTAG Boundary Scan for BGA and f BGA packages - “ZZ” Sleep Mode option Functional Description[1] The CY7C1361C/CY7C1363C is a 3.3V, 256K x 36 and 512K x 18 Synchronous Flowthrough SRAMs, respectively designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133-MHz version). A 2-bit on-chip counter captures the first address in a burst and increments the address automatically for the rest of the burst access. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). The synchronous inputs include all addresses, all data inputs, address-pipelining Chip Enable (CE1), depth-expansion Chip Enables (CE2 and CE3[2]), Burst Control inputs (ADSC, ADSP, and ADV), Write Enables (BWx, and BWE), and Global Write (GW). Asynchronous inputs include the Output Enable (OE) and the ZZ pin. The CY7C1361C/CY7C1363C allows either interleaved or linear burst sequences, selected by the MODE input pin. A HIGH selects an interleaved burst sequence, while a LOW selects a linear burst sequence. Burst accesses can be initiated with the Processor Address Strobe (ADSP) or the cache Controller Address Strobe (ADSC) inputs. Address advancement is controlled by the...