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Cypress Semiconductor Electronic Components Datasheet

CY7C1363D Datasheet

9-Mbit Flow-Through SRAM

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CY7C1363D
9-Mbit (512K × 18) Flow-Through SRAM
9-Mbit (512K × 18) Flow-Through SRAM
Features
Supports 133 MHz bus operations
512K × 18 common I/O
3.3 V – 5% and +10% core power supply (VDD)
2.5 V or 3.3 V I/O power supply (VDDQ)
Fast clock-to-output times
6.5 ns (133-MHz version)
Provide high performance 2-1-1-1 access rate
User-selectable burst counter supporting IntelPentium
interleaved or linear burst sequences
Separate processor and controller address strobes
Synchronous self-timed write
Asynchronous output enable
Available in Pb-free 100-pin TQFP package
TQFP available with 3-chip enable
“ZZ” sleep mode option
Functional Description
The CY7C1363D is a 3.3 V, 512K × 18 synchronous flow-through
SRAM, respectively designed to interface with high speed
microprocessors with minimum glue logic. Maximum access
delay from clock rise is 6.5 ns (133 MHz version). A 2-bit on-chip
counter captures the first address in a burst and increments the
address automatically for the rest of the burst access. All
synchronous inputs are gated by registers controlled by a
positive-edge-triggered clock input (CLK). The synchronous
inputs include all addresses, all data inputs, address-pipelining
CchEip3[1e])n, abbulerst(CcEon1)t,rodl einppthu-tesxp(AanDsSioCn,
chip enables (CE2 and
ADSP, and ADV), write
enables (BWx, and BWE), and global write (GW). Asynchronous
inputs include the output enable (OE) and the ZZ pin.
The CY7C1363D enables either interleaved or linear burst
sequences, selected by the MODE input pin. A HIGH selects an
interleaved burst sequence, while a LOW selects a linear burst
sequence. Burst accesses can be initiated with the processor
address strobe (ADSP) or the cache controller address strobe
(ADSC) inputs. Address advancement is controlled by the
address advancement (ADV) input.
Addresses and chip enables are registered at rising edge of
clock when either address strobe processor (ADSP) or address
strobe controller (ADSC) are active. Subsequent burst
addresses can be internally generated as controlled by the
advance pin (ADV).
The CY7C1363D operates from a +3.3 V core power supply
while all outputs may operate with either a +2.5 or +3.3 V supply.
All inputs and outputs are JEDEC-standard
JESD8-5-compatible.
For a complete list of related documentation, click here.
Selection Guide
Maximum access time
Maximum operating current
Maximum CMOS standby current
Description
Industrial
133 MHz
6.5
250
40
Unit
ns
mA
mA
Note
1. CE3 is for A version of 100-pin TQFP (3 Chip Enable Option).
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-86215 Rev. *D
• San Jose, CA 95134-1709 • 408-943-2600
Revised June 23, 2016


Cypress Semiconductor Electronic Components Datasheet

CY7C1363D Datasheet

9-Mbit Flow-Through SRAM

No Preview Available !

CY7C1363D
Logic Block Diagram – CY7C1363D
A 0,A1,A
MODE
ADV
CLK
ADSC
ADSP
BW B
BW A
BWE
GW
CE 1
CE 2
CE 3
OE
ZZ
ADDRESS
REGISTER
A[1:0]
BURST Q1
COUNTER AND
LOGIC
CLR Q0
DQ B,DQP B
WRITE REGISTER
DQ A,DQP A
WRITE REGISTER
ENABLE
REGISTER
SLEEP
CONTROL
DQ B,DQP B
WRITE DRIVER
DQ A,DQP A
WRITE DRIVER
MEMORY
ARRAY
SENSE
AMPS
OUTPUT
BUFFERS
DQs
DQP A
DQP B
INPUT
REGISTERS
Document Number: 001-86215 Rev. *D
Page 2 of 22


Part Number CY7C1363D
Description 9-Mbit Flow-Through SRAM
Maker Cypress Semiconductor
Total Page 22 Pages
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