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Cypress Semiconductor Electronic Components Datasheet

CY7C1370KVE33 Datasheet

18-Mbit (512K x 36/1M x 18) Pipelined SRAM

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CY7C1370KV33/CY7C1370KVE33
CY7C1372KV33/CY7C1372KVE33
18-Mbit (512K × 36/1M × 18) Pipelined SRAM
with NoBL™ Architecture (With ECC)
18-Mbit (512K × 36/1M × 18) Pipelined SRAM with NoBL™ Architecture (With ECC)
Features
Pin-compatible and functionally equivalent to ZBT™
Supports 250-MHz bus operations with zero wait states
Available speed grades are 250, 200, and 167 MHz
Internally self-timed output buffer control to eliminate the need
to use asynchronous OE
Fully registered (inputs and outputs) for pipelined operation
Byte write capability
3.3 V core power supply (VDD)
3.3 V/2.5 V I/O power supply (VDDQ)
Fast clock-to-output times
2.5 ns (for 250 MHz device)
Clock enable (CEN) pin to suspend operation
Synchronous self-timed writes
Available in JEDEC-standard Pb-free 100-pin TQFP, Pb-free
165-ball FBGA package
IEEE 1149.1 JTAG-compatible boundary scan
Burst capability – linear or interleaved burst order
“ZZ” sleep mode option and stop clock option
On chip Error Correction Code (ECC) to reduce Soft Error Rate
(SER)
Functional Description
The CY7C1370KV33/CY7C1370KVE33/CY7C1372KV33/
CY7C1372KVE33 are 3.3 V, 512K × 36 and 1M × 18
synchronous pipelined burst SRAMs with No Bus Latency™
(NoBL logic, respectively. They are designed to support
unlimited true back-to-back read/write operations with no wait
states. The CY7C1370KV33/CY7C1370KVE33/
CY7C1372KV33/CY7C1372KVE33 are equipped with the
advanced (NoBL) logic required to enable consecutive
read/write operations with data being transferred on every clock
cycle. This feature dramatically improves the throughput of data
in systems that require frequent write/read transitions. The
CY7C1370KV33/CY7C1370KVE33/CY7C1372KV33/
CY7C1372KVE33 are pin compatible and functionally equivalent
to ZBT devices.
All synchronous inputs pass through input registers controlled by
the rising edge of the clock. All data outputs pass through output
registers controlled by the rising edge of the clock. The clock
input is qualified by the clock enable (CEN) signal, which when
deasserted suspends operation and extends the previous clock
cycle.
Write operations are controlled by the byte write selects
(BWa–BWd for CY7C1370KV33/CY7C1370KVE33 and
BWa–BWb for CY7C1372KV33/CY7C1372KVE33) and a write
enable (WE) input. All writes are conducted with on-chip
synchronous self-timed write circuitry.
Three synchronous chip enables (CE1, CE2, CE3) and an
asynchronous output enable (OE) provide for easy bank
selection and output tri-state control. In order to avoid bus
contention, the output drivers are synchronously tristated during
the data portion of a write sequence.
Selection Guide
Maximum access time
Maximum operating current
Description
250 MHz 200 MHz 167 MHz Unit
2.5 3.0 3.4 ns
× 18 180
× 36 200
158
178
143
163
mA
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-97836 Rev. *G
• San Jose, CA 95134-1709 • 408-943-2600
Revised August 9, 2016


Cypress Semiconductor Electronic Components Datasheet

CY7C1370KVE33 Datasheet

18-Mbit (512K x 36/1M x 18) Pipelined SRAM

No Preview Available !

CY7C1370KV33/CY7C1370KVE33
CY7C1372KV33/CY7C1372KVE33
Logic Block Diagram – CY7C1370KV33
A0, A1, A
MODE
CLK C
CEN
ADV/LD
BW a
BW b
BW c
BW d
WE
ADDRESS
REGISTER 0
WRITE ADDRESS
REGISTER 1
A1 D1
Q1 A1'
A0 D0 BURST Q0 A0'
LOGIC
ADV/LD
C
WRITE ADDRESS
REGISTER 2
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
WRITE
DRIVERS
MEMORY
ARRAY
S
E
N
S
E
A
M
P
S
O
U
T
P
U
T
R
E
G
I
S
T
E
R
S
E
D
A
T
A
S
T
E
E
R
I
N
O
U
T
P
U
T
B
U
F
F
E
R
S
E
G
INPUT
REGISTER 1 E
INPUT
REGISTER 0 E
OE
CE1 READ LOGIC
CE2
CE3
ZZ SLEEP
CONTROL
DQ s
DQ Pa
DQ Pb
DQ Pc
DQ Pd
Logic Block Diagram – CY7C1370KVE33
A0, A1, A
MODE
CLK C
CEN
ADV/LD
BWA
BWB
BWC
BWD
WE
ADDRESS
REGISTER 0
WRITE ADDRESS
REGISTER 1
A1 D1
Q1 A1'
A0 D0 BURST Q0 A0'
LOGIC
ADV/LD
C
WRITE ADDRESS
REGISTER 2
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
WRITE
DRIVERS
ECC
ENCODER
MEMORY
ARRAY
S
E
N
S
E
A
M
P
S
O
U
T
P
U
T
R
E
G
I
S
T
E
R
S
E
D
A
T
A
S
T
E
E
R
I
N
E
C
C
D
E
C
O
D
E
R
O
U
T
P
U
T
B
U
F
F
E
R
S
E
G
INPUT
REGISTER 1 E
INPUT
REGISTER 0 E
DQs
DQPA
DQPB
DQPC
DQPD
OE
CE1 READ LOGIC
CE2
CE3
ZZ SLEEP
CONTROL
Document Number: 001-97836 Rev. *G
Page 2 of 32


Part Number CY7C1370KVE33
Description 18-Mbit (512K x 36/1M x 18) Pipelined SRAM
Maker Cypress Semiconductor
Total Page 30 Pages
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