CY7C1461KV33
Key Features
- No Bus Latency™ (NoBL™) architecture eliminates dead cycles between write and read cycles
- Supports up to 133 MHz bus operations with zero wait states ❐ Data is transferred on every clock
- Internally self timed output buffer control to eliminate the need to use OE
- Registered inputs for flow through operation
- 3.3 V and 2.5 V I/O power supply
- Fast clock-to-output times ❐ 6.5 ns (for 133-MHz device)
- Clock Enable (CEN) pin to enable clock and suspend operation
- Synchronous self timed writes
- Asynchronous Output Enable
- CY7C1461KV33
