* No Bus Latency™ (NoBL™) architecture eliminates dead cycles between write and read cycles
* Supports up to 133 MHz bus operations with zero wait states
* Data is transferred on every clock
* Pin compatible and functionally equivalent to ZBT™ devices
* Internally self timed o
CY7C1461KV33 Datasheet (954.99 KB)
CY7C1461KV33
Cypress Semiconductor
954.99 KB
36-mbit (1m x 36/2m x 18) flow-through sram.
CY7C1461KV33 CY7C1463KV33 36-Mbit (1M × 36/2M × 18) Flow-Through SRAM with NoBL™ Architecture 36-Mbit (1M × 36/2M × 18) Flow-Through SRAM with NoBL™ .
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