CY7C1510AV18

The CY7C1510AV18 is 72-Mbit QDR-II SRAM 2-Word Burst Architecture designed by Cypress Semiconductor.

Product Overview

Cypress Semiconductor

Datasheet Details

Part number	CY7C1510AV18
Manufacturer	Cypress Semiconductor
File Size	690.83 KB
Description	72-Mbit QDR-II SRAM 2-Word Burst Architecture
Datasheet	CY7C1510AV18_CypressSemiconductor.pdf
Additional preview pages of the CY7C1510AV18 datasheet.

Product details

Description

Maximum Operating Frequency Maximum Operating Current x8 x9 x18 x36 250 MHz 250 1230 1240 1350 1560 Configurations CY7C1510AV18 8M x 8 CY7C1525AV18 8M x 9 CY7C1512AV18 4M x 18 CY7C1514AV18 2M x 36 Functional Description The CY7C1510AV18, CY7C1525AV18, CY7C1512AV18, and CY7C1514AV18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR™-II architecture.QDR-II architecture consists of two separate ports: the read port and the write port to access

Features

Separate independent read and write data ports.
Supports concurrent transactions.
250 MHz clock for high bandwidth.
2-word burst on all accesses.
Double Data Rate (DDR) interfaces on both read and write ports (data transferred at 500 MHz) at 250 MHz.
Two input clocks (K and K) for precise DDR timing.
SRAM uses rising edges only.
Two input clocks for output data (C and C) to minimize clock skew and flight time mismatches.
Echo clocks (CQ and CQ) simpl.

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Other Datasheets by Cypress Semiconductor

CY7C1510V18 - 1.8V Synchronous Pipelined SRAM
CY7C1511AV18 - 72-Mbit QDR-II SRAM 4-Word Burst Architecture
CY7C1511JV18 - 72-Mbit QDR-II SRAM 4-Word Burst Architecture
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Published: Mar 25, 2010 |