CY7C1511JV18 - 72-Mbit QDR-II SRAM 4-Word Burst Architecture

Cypress Semiconductor

Datasheet Details

Part number	CY7C1511JV18
Manufacturer	Cypress Semiconductor
File Size	719.20 KB
Description	72-Mbit QDR-II SRAM 4-Word Burst Architecture
Datasheet	CY7C1511JV18_CypressSemiconductor.pdf

The CY7C1511JV18, CY7C1526JV18, CY7C1513JV18, and CY7C1515JV18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR-II architecture.

Configurations CY7C1511JV18.
8M x 8 CY7C1526JV18.
8M x 9 CY7C1513JV18.
4M x 18 CY7C1515JV18.
2M x 36 Separate independent read and write data ports.
Supports concurrent transactions 300 MHz clock for high bandwidth 4-word burst for reducing address bus frequency Double Data Rate (DDR) interfaces on both read and write ports (data transferred at 600 MHz) at 300 MHz Two input clocks (K and K) for precise DDR timing.
SRAM uses rising edges only.

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Published: Dec 3, 2013 |