Datasheet4U Logo Datasheet4U.com

CY7C15632KV18 - 72-Mbit QDR II+ SRAM Four-Word Burst Architecture

Features

  • Separate Independent Read and Write Data Ports.
  • Supports concurrent transactions.
  • 500 MHz Clock for High Bandwidth.
  • Four-word Burst for Reducing Address Bus Frequency.
  • Double Data Rate (DDR) Interfaces on both Read and Write Ports (data transferred at 1000 MHz) at 500 MHz.
  • Available in 2.5 Clock Cycle Latency.
  • Two Input Clocks (K and K) for precise DDR Timing.
  • SRAM uses rising edges only.
  • Echo Clocks (CQ and CQ) simplify Data Capture in High Speed Sy.

📥 Download Datasheet

📁 Similar Datasheet

  • CY7C1518AV18 - 72-Mbit DDR-II SRAM (Cypress)
  • CY7C1520AV18 - 72-Mbit DDR-II SRAM (Cypress)
  • CY7C1006D - 1-Mbit (256K x 4) Static RAM (Cypress)
  • CY7C1011G - 2-Mbit (128K words x 16 bit) Static RAM (Cypress)
  • CY7C1041G - 4-Mbit (256K words x 16 bit) Static RAM (Cypress)
  • CY7C1041GE - 4-Mbit (256K words x 16 bit) Static RAM (Cypress)
  • CY7C1041GN - 4-Mbit (256K words x 16 bit) Static RAM (Cypress)
  • CY7C1049GN - 4-Mbit (512K words x 8 bit) Static RAM (Cypress)
  • CY7C1061DV33 - 16-Mbit (1 M X 16) Static RAM (Cypress)
  • CY7C1061G - 16-Mbit (1 M words x 16 bit) Static RAM (Cypress)
Other Datasheets by Cypress Semiconductor
  • CY7C1563XV18 - 72-Mbit QDR II+ Xtreme SRAM Four-Word Burst Architecture
  • CY7C1562XV18 - 72-Mbit QDR II+ Xtreme SRAM Two-Word Burst Architecture
  • CY7C1564XV18 - 72-Mbit QDR II+ Xtreme SRAM Two-Word Burst Architecture
  • CY7C1565KV18 - 72-Mbit QDR II+ SRAM Four-Word Burst Architecture
  • CY7C1565XV18 - 72-Mbit QDR II+ Xtreme SRAM Four-Word Burst Architecture
  • CY7C1568KV18 - 72-Mbit DDR II+ SRAM Two-Word Burst Architecture
  • CY7C150 - 1Kx4 Static RAM
  • CY7C1510AV18 - 72-Mbit QDR-II SRAM 2-Word Burst Architecture

Full PDF Text Transcription

Click to expand full text
CY7C15632KV18 72-Mbit QDR® II+ SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) 72-Mbit QDR® II+ SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) Features ■ Separate Independent Read and Write Data Ports ❐ Supports concurrent transactions ■ 500 MHz Clock for High Bandwidth ■ Four-word Burst for Reducing Address Bus Frequency ■ Double Data Rate (DDR) Interfaces on both Read and Write Ports (data transferred at 1000 MHz) at 500 MHz ■ Available in 2.
Published: |