CY7C1562XV18 - 72-Mbit QDR II+ Xtreme SRAM Two-Word Burst Architecture

Datasheet Summary

Features

Separate independent read and write data ports.
Supports concurrent transactions.
450 MHz clock for high bandwidth.
Two-word burst for reducing address bus frequency.
Double Data Rate (DDR) interfaces on both read and write ports (data transferred at 900 MHz) at 450 MHz.
Available in 2.5 clock cycle latency.
Two input clocks (K and K) for precise DDR timing.
SRAM uses rising edges only.
Echo clocks (CQ and CQ) simplify data capture in high speed syst.

Cypress Semiconductor

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Datasheet Details

Part number	CY7C1562XV18
Manufacturer	Cypress Semiconductor
File Size	1.20 MB
Description	72-Mbit QDR II+ Xtreme SRAM Two-Word Burst Architecture
Datasheet	CY7C1562XV18 Datasheet
Additional preview pages of the CY7C1562XV18 datasheet.

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CY7C1562XV18/CY7C1564XV18 72-Mbit QDR® II+ Xtreme SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) 72-Mbit QDR® II+ Xtreme SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) Features ■ Separate independent read and write data ports ❐ Supports concurrent transactions ■ 450 MHz clock for high bandwidth ■ Two-word burst for reducing address bus frequency ■ Double Data Rate (DDR) interfaces on both read and write ports (data transferred at 900 MHz) at 450 MHz ■ Available in 2.

Published: Mar 14, 2017 |