CY7C15632KV18 - 72-Mbit QDR II+ SRAM Four-Word Burst Architecture

Datasheet Summary

Features

Separate Independent Read and Write Data Ports.
Supports concurrent transactions.
500 MHz Clock for High Bandwidth.
Four-word Burst for Reducing Address Bus Frequency.
Double Data Rate (DDR) Interfaces on both Read and Write Ports (data transferred at 1000 MHz) at 500 MHz.
Available in 2.5 Clock Cycle Latency.
Two Input Clocks (K and K) for precise DDR Timing.
SRAM uses rising edges only.
Echo Clocks (CQ and CQ) simplify Data Capture in High Speed Sy.

Cypress Semiconductor

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Datasheet Details

Part number	CY7C15632KV18
Manufacturer	Cypress Semiconductor
File Size	427.43 KB
Description	72-Mbit QDR II+ SRAM Four-Word Burst Architecture
Datasheet	CY7C15632KV18 Datasheet
Additional preview pages of the CY7C15632KV18 datasheet.

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CY7C15632KV18 72-Mbit QDR® II+ SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) 72-Mbit QDR® II+ SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) Features ■ Separate Independent Read and Write Data Ports ❐ Supports concurrent transactions ■ 500 MHz Clock for High Bandwidth ■ Four-word Burst for Reducing Address Bus Frequency ■ Double Data Rate (DDR) Interfaces on both Read and Write Ports (data transferred at 1000 MHz) at 500 MHz ■ Available in 2.

Published: Mar 14, 2017 |