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Cypress Semiconductor Electronic Components Datasheet

CY7C371 Datasheet

32-Macrocell Flash CPLD

No Preview Available !

7c371: Tuesday, May 26, 1992
Revision: August 9, 1995
CY7C371
tUltraLogic 32ĆMacrocell Flash CPLD
Features
D 32 macrocells in two logic blocks
D 32 I/O pins
D 6 dedicated inputs including 2 clock
pins
D No hidden delays
D High speed
Ċ fMAX = 143 MHz
Ċ tPD= 8.5 ns
Ċ tS = 5 ns
Ċ tCO= 6 n s
D Electrically alterable FLASH
technology
D Available in 44Ćpin PLCC, CLCC, and
TQFP packages
D Pin compatible with the CY7C372
Functional Description
The CY7C371 is a Flash erasable Complex
Programmable Logic Device (CPLD) and
is part of the FLASH370 family of highĆdenĆ
sity, highĆspeed CPLDs. Like all members
of the FLASH370 family, the CY7C371 is
designed to bring the ease of use and high
performance of the 22V10 to highĆdensity
CPLDs.
The 32 macrocells in the CY7C371 are diĆ
vided between two logic blocks. Each logic
block includes 16 macrocells, a 72 x 86
product term array, and an intelligent
product term allocator.
The logic blocks in the FLASH370 architecĆ
ture are connected with an extremely fast
and predictable routing resourceĊthe
Programmable Interconnect Matrix
(PIM). The PIM brings flexibility, routĆ
ability, speed, and a uniform delay to the
interconnect.
Like all members of the FLASH370 family,
the CY7C371 is rich in I/O resources.
Each macrocell in the device features an
associated I/O pin, resulting in 32 I/O pins
on the CY7C371. In addition, there are
four dedicated inputs and two input/clock
pins.
Finally, the CY7C371 features a very simĆ
ple timing model. Unlike other highĆdenĆ
sity CPLD architectures, there are no hidĆ
den speed delays such as fanout effects, inĆ
terconnect delays, or expander delays. ReĆ
gardless of the number of resources used
or the type of application, the timing paĆ
rameters on the CY7C371 remain the
same.
Logic Block Diagram
INPUTS
4
INPUT
MACROCELLS
CLOCK
INPUTS
2
INPUT/CLOCK
MACROCELLS
16 I/Os
I/O0-I/O15
2
LOGIC
BLOCK
A
16
PIM
36
16
2
36
16
LOGIC
BLOCK
B
16
7c371Ć1
16 I/Os
I/O16-I/O31
Selection Guide
7C371-143
Maximum Propagation Delay, tPD (ns)
Minimum SetĆUp, tS (ns)
Maximum Clock to Output, tCO (ns)
Maximum Supply
Current, ICC (mA)
Commercial
Military/Ind.
Shaded area contains preliminary information.
8.5
5
6
220
7C371-110
10
6
6.5
175
7C371-83
12
10
10
175
220
7C371L-83
12
10
10
90
110
7C371-66
15
12
12
175
220
7C371L-66
15
12
12
90
110
DCypress Semiconductor Corporation
3901 North First Street
1
DSa
D Dn Jose
C A 95134
408-943-2600
December 1993 - Revised August 1995
http://www.Datasheet4U.com/


Cypress Semiconductor Electronic Components Datasheet

CY7C371 Datasheet

32-Macrocell Flash CPLD

No Preview Available !

7c371: Tuesday, May 26, 1992
Revision: August 9, 1995
Pin Configurations
PLCC/CLCC
Top View
I/O5
I/O6
I/O7
I0
I1
GND
CLK0/I2
I/O8
I/O9
I/O10
I/O11
6 5 4 3 2 1 44 43 42 41 40
39
7
38
8
9
10
11
12
37
36
35
34
33
13
32
14
31
15
16
30
29
17
18 19 20 21 22 23 24 25 26 27 28
I/O27
I/O26
I/O25
I/O24
CLK1/I5
GND
I4
I3
I/O23
I/O22
I/O21
7c371Ć2
TQFP
Top View
CY7C371
I/O5
I/O6
I/O7
I0
I1
GND
CLK0/I2
I/O8
I/O9
I/O10
I/O11
44 43 42 41 40 39 38 37 36 35 34
1 33
2 32
3 31
4 30
5 29
6 28
7 27
8 26
9 25
10
24
11
23
12 13 14 15 16 17 18 19 20 21 22
I/O27
I/O26
I/O25
I/O24
CLK1/I5
GND
I4
I3
I/O23
I/O22
I/O21
7c371Ć3
Logic Block
The number of logic blocks distinguishes the members of the
FLASH370 family. The CY7C371 includes two logic blocks. Each
logic block is constructed of a product term array, a product term
allocator, and 16 macrocells.
Product Term Array
The product term array in the FLASH370 logic block includes 36 inĆ
puts from the PIM and outputs 86 product terms to the product
term allocator. The 36 inputs from the PIM are available in both
positive and negative polarity, making the overall array size 72 x 86.
This large array in each logic block allows for very complex funcĆ
tions to be implemented in a single pass through the device.
Product Term Allocator
The product term allocator is a dynamic, configurable resource
that shifts product terms to macrocells that require them. Any
number of product terms between 0 and 16 inclusive can be asĆ
signed to any of the logic block macrocells (this is called product
term steering). Furthermore, product terms can be shared among
multiple macrocells. This means that product terms that are comĆ
mon to more than one output can be implemented in a single prodĆ
uct term. Product term steering and product term sharing help to
increase the effective density of the FLASH370 CPLDs. Note that
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines,
not tested.)
Storage Temperature . . . . . . . . . . . . . . . . . . . -65_C to +150_C
Ambient Temperature with
Power Applied . . . . . . . . . . . . . . . . . . . . . . . . -55_C to +125_C
Supply Voltage to Ground Potential . . . . . . . . . -0.5V to +7.0V
DC Voltage Applied to Outputs
in High Z State . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +7.0V
DC Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +7.0V
DC Program Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.5V
Output Current into Outputs (LOW) . . . . . . . . . . . . . . . 16 mA
product term allocation is handled by software and is invisible to
the user.
I/O Macrocell
Each of the macrocells on the CY7C371 has a separate associated
I/O pin. The input to the macrocell is the sum of between 0 and 16
product terms from the product term allocator. The macrocell inĆ
cludes a register that can be optionally bypassed. It also has polarĆ
ity control, and two global clocks to trigger the register. The maĆ
crocell also features a separate feedback path to the PIM so that
the register can be buried if the I/O pin is used as an input.
Programmable Interconnect Matrix
The Programmable Interconnect Matrix (PIM) connects the two
logic blocks on the CY7C371 to the inputs and to each other. All
inputs (including feedbacks) travel through the PIM. There is no
speed penalty incurred by signals traversing the PIM.
Design Tools
Warp2 Warp2+ Warp3Development software for the CY7C371 is available from CyĆ
press's
,
, and
software packages. All of these
products are based on the IEEEĆstandard VHDL language. CyĆ
press also actively supports thirdĆparty design tools such as
ABELt, CUPLt, MINC, and LOG/iCt. Please contact your loĆ
cal Cypress representative for further information.
Static Discharge Voltage . . . . . . . . . . . . . . . . . . . . . . . . >2001V
(per MILĆSTDĆ883, Method 3015)
LatchĆUp Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . >200 mA
Operating Range
Range
Commercial
Military[1]
Industrial
Ambient
Temperature
0_C to +70_C
-55_C to +125_C
-40_C to +85_C
VCC
5V ± 5%
5V ± 10%
5V ± 10%
Note:
1. TA is the instant on" case temperature.
2
http://www.Datasheet4U.com/


Part Number CY7C371
Description 32-Macrocell Flash CPLD
Maker Cypress Semiconductor
Total Page 11 Pages
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