CY9B400A Datasheet | Cypress

32-bit Arm® Cortex®-M3 Core - Processor version: r2p0 - Up to 80 MHz Frequency Operation - Memory Protection Unit (MPU): improve the reliability of an embedded system - Integrated Nested Vectored Interrupt Controller (NVIC): 1 NMI (non-maskable interrupt) and 48 peripheral interrupts and 16 priority levels - 24-bit System timer (Sys Tick): System timer for OS task management On-chip Memories [Flash memory] - Up to 512 Kbyte - Read cycle: 0wait-cycle@up to 60 MHz, 2wait-cycle- above - : Instruction pre-fetch buffer is included. So when CPU access continuously, it bees 0wait-cycle - Security function for code protection [SRAM] This series contain a total of up to 64 Kbyte on-chip SRAM. This is posed of two independent SRAM (SRAM0, SRAM1). SRAM0 is connected to I-code bus and D-code bus of Cortex-M3 core. SRAM1 is connected to System bus. - SRAM0: Up to 32 Kbyte - SRAM1: Up to 32 Kbyte CAN Interface (Max. 2 channels) - patible with CAN Specification 2.0A/B - Maximum transfer rate: 1 Mbps - Built-in 32 message buffer Multi-function Serial Interface (Max. 8 channels) - 4 channels with 16steps × 9bit FIFO (ch.4-ch.7), 4 channels without FIFO (ch.0-ch.3) - Operation mode is selectable from the followings for each channel.  UART  CSIO  LIN  I2C [UART] - Full-duplex double buffer - Selection with or without parity supported - Built-in dedicated baud rate generator - External clock available as a serial...