CY91520
Features
FR81S CPU Core
- 32-bit RISC, load/store architecture, pipeline 5-stage structure
- Maximum operating frequency: 80 MHz (Source oscillation = 4.0 MHz and 20 multiplied (PLL clock multiplication system))
- General-purpose register : 32 bits × 16 sets
- 16-bit fixed length instructions (basic instruction), 1 instruction per cycle
- Instructions appropriate to embedded applications Memory-to-memory transfer instruction Bit processing instruction Barrel shift order etc.
- High-level language support instructions
- Function entry/exit instructions
- Register content multi-load and store instructions
- Bit search instructions Logical 1 detection, 0 detection, and change-point detection
- Branch instructions with delay slot
- Overhead reduction during branch process
- Register interlock function
- Easy assembler writing
- The support at the built-in / instruction level of the multiplier
- Signed 32-bit multiplication: 5 cycles
- Signed 16-bit multiplication: 3 cycles
-...
