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Cypress Semiconductor Electronic Components Datasheet

CYW15G0401DXB Datasheet

Transceiver

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CYP15G0401DXB
CYV15G0401DXB
CYW15G0401DXB
Quad HOTLink II™ Transceiver
Features
• Second-generation HOTLink® technology
• Compliant to multiple standards
— ESCON, DVB-ASI, Fibre Channel and Gigabit
Ethernet (IEEE802.3z)
— CPRI™ compliant
www.DataSheet4U.coCmYW15G0401DXB compliant to OBSAI-RP3
— CYV15G0401DXB compliant to SMPTE 259M and
SMPTE 292M
— 8B/10B encoded or 10-bit unencoded data
• Quad channel transceiver operates from 195 to
1500 MBaud serial data rate
— CYW15G0401DXB operates from 195 to 1540 MBaud
— Aggregate throughput of 12 GBits/second
• Selectable parity check/generate
• Selectable multi-channel bonding options
— Four 8-bit channels
— Two 16-bit channels
— One 32-bit channel
— N x 32-bit channel support (inter-chip)
• Skew alignment support for multiple bytes of offset
• Selectable input/output clocking options
• MultiFrame™ Receive Framer
— Bit and Byte alignment
— Comma or full K28.5 detect
— Single- or multi-byte framer for byte alignment
— Low-latency option
• Synchronous LVTTL parallel interface
• Optional Elasticity Buffer in Receive Path
• Optional Phase Align Buffer in Transmit Path
• Internal phase-locked loops (PLLs) with no external
PLL components
• Dual differential PECL-compatible serial inputs per
channel
— Internal DC-restoration
• Dual differential PECL-compatible serial outputs per
channel
Source matched for 50transmission lines
— No external bias resistors required
— Signaling-rate controlled edge-rates
• Compatible with
— fiber-optic modules
— copper cables
— circuit board traces
• JTAG boundary scan
• Built-In Self-Test (BIST) for at-speed link testing
• Per-channel Link Quality Indicator
— Analog signal detect
— Digital signal detect
• Low power 2.5W @ 3.3V typical
• Single 3.3V supply
• 256-ball thermally enhanced BGA
• Pb-free package option available
0.25µ BiCMOS technology
Functional Description
The CYP(V)15G0401DXB[1] Quad HOTLink II™ Transceiver
is a point-to-point or point-to-multipoint communications
building block allowing the transfer of data over high-speed
serial links (optical fiber, balanced, and unbalanced copper
transmission lines) at signaling speeds ranging from
195-to-1500 MBaud per serial link.
10
10
Serial Links
10
10
10
10
Serial Links
10
10
10
10
Serial Links
10
10
10
10
Serial Links
Backplane or
Cabled
Connections
10
10
Figure 1. HOTLink II System Connections
Note:
1. CYV15G0401DXB refers to SMPTE 259M and SMPTE 292M compliant devices. CYW15G0401DXB refers to OBSAI RP3 compliant devices (maximum
operating data rate is 1540 MBaud). CYP15G0401DXB refers to devices not compliant to SMPTE 259M and SMPTE 292M pathological test requirements and
also OBSAI RP3 operating datarate of 1536 MBaud. CYP(V)(W)15G0401DXB refers to all three devices.
Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600
Document #: 38-02002 Rev. *L
Revised March 30, 2005


Cypress Semiconductor Electronic Components Datasheet

CYW15G0401DXB Datasheet

Transceiver

No Preview Available !

CYP15G0401DXB
CYV15G0401DXB
CYW15G0401DXB
The CYW15G0401DXB[1] operates from 195 to 1540 MBaud,
which includes operation at the OBSAI RP3 datarate of both
1536 MBaud and 768 MBaud.
The CYV15G0401DXB satisfies the SMPTE 259M and
SMPTE 292M compliance as per the EG34-1999 Pathological
Test Requirements.
The multiple channels in each device may be combined to
allow transport of wide buses across significant distances with
minimal concern for offsets in clock phase or link delay. Each
transmit channel accepts parallel characters in an Input
Register, encodes each character for transport, and converts
it to serial data. Each receive channel accepts serial data and
converts it to parallel data, decodes the data into characters,
and presents these characters to an Output Register. Figure 1
www.DataSheeti4lluUs.ctroamtes typical connections between independent host
systems and corresponding CYP15G0401DXB parts.
As a second-generation HOTLink device, the
CYP(V)(W)15G0401DXB extends the HOTLink family with
enhanced levels of integration and faster data rates, while
maintaining serial-link compatibility (data, command, and
BIST) with other HOTLink devices. The transmit (TX) section
of the CYP(V)(W)15G0401DXB Quad HOTLink II consists of
four byte-wide channels that can be operated independently
or bonded to form wider buses. Each channel can accept
either eight-bit data characters or pre-encoded 10-bit trans-
mission characters. Data characters are passed from the
Transmit Input Register to an embedded 8B/10B Encoder to
improve their serial transmission characteristics. These
encoded characters are then serialized and output from dual
Positive ECL (PECL)-compatible differential transmission-line
drivers at a bit-rate of either 10- or 20-times the input reference
clock.
The receive (RX) section of the CYP(V)(W)15G0401DXB
Quad HOTLink II consists of four byte-wide channels that can
be operated independently or synchronously bonded for
greater bandwidth. Each channel accepts a serial bit-stream
from one of two PECL-compatible differential line receivers
and, using a completely integrated PLL Clock Synchronizer,
recovers the timing information necessary for data recon-
struction. Each recovered serial stream is deserialized and
framed into characters, 8B/10B decoded, and checked for
transmission errors. Recovered decoded characters are then
written to an internal Elasticity Buffer, and presented to the
destination host system. The integrated 8B/10B
Encoder/Decoder may be bypassed for systems that present
externally encoded or scrambled data at the parallel interface.
For those systems using buses wider than a single byte, the
four independent receive paths can be bonded together to
allow synchronous delivery of data across a two-byte-wide
(16-bit) path, or across all four bytes (32-bit). Multiple
CYP(V)(W)15G0401DXB devices may be bonded together to
provide synchronous transport of buses wider than 32 bits.
The parallel I/O interface may be configured for numerous
forms of clocking to provide the highest flexibility in system
architecture. In addition to clocking the transmit path, the
receive interface may be configured to present data relative to
a recovered clock or to a local reference clock.
Each transmit and receive channel contains an independent
BIST pattern generator and checker. This BIST hardware
allows at-speed testing of the high-speed serial data paths in
each transmit and receive section, and across the intercon-
necting links.
HOTLink II devices are ideal for a variety of applications where
parallel interfaces can be replaced with high-speed,
point-to-point serial links. Some applications include
interconnecting backplanes on switches, routers, servers and
video transmission systems.
The CYV15G0401DXB is verified by testing to be compliant to
all the pathological test patterns documented in SMPTE
EG34-1999, for both the SMPTE 259M and 292M signaling
rates. The tests ensure that the receiver recovers data with no
errors for the following patterns:
1. Repetitions of 20 ones and 20 zeros.
2. Single burst of 44 ones or 44 zeros.
3. Repetitions of 19 ones followed by 1 zero or 19 zeros fol-
lowed by 1 one.
Document #: 38-02002 Rev. *L
Page 2 of 53


Part Number CYW15G0401DXB
Description Transceiver
Maker Cypress Semiconductor
Total Page 30 Pages
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