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Cypress Semiconductor Electronic Components Datasheet

CYW2331 Datasheet

Dual Serial Input PLL

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1CYW2331
PRELIMINARY
CYW2331
Dual Serial Input PLL with 2.0-GHz and 600-MHz Prescalers
Features
• Operating voltage: 2.7V to 5.5V
• PLL1 operating frequency:
— 2.0 GHz with prescaler ratios of 64/65 and 128/129
• PLL2 operating frequency:
— 600 MHz with prescaler ratios of 8/9 and 16/17
• Lock detect feature
• Available in a 20-pin TSSOP (Thin Shrink Small Outline
Package)
www.DataSheet4UA.cvoamilable in a 24-pin CSP (Chip Scale Package)
• Available in a 20-pin MLF
(Mirco Lead Frame Package)
Applications
The Cypress CYW2331 is a dual serial input PLL frequency
synthesizer which includes a 2.0-GHz RF and a 600-MHz IF
dual modulus prescaler to combine the RF and IF mixer fre-
quency sections of wireless communication systems. The syn-
thesizer is designed for cordless/cellular telephone systems,
cable TV tuners, WLANs and other wireless communication
systems. The device operates from 2.7V and dissipates only
24 mW.
CYW2331 Dual Hi-Lo PLL Block Diagram
GND (4)
GND (7)
VCC1 (1) VCC2 (20) VP1 (2)
FIN1 (5)
FIN1# (6)
Prescaler
64/65 or
128/129
Binary 7-Bit
Swallow Counter
Binary 11-Bit
fp1
Programmable Counter
Phase
Detector
Charge
Pump
DOPLL1 (3)
OSC_IN (8)
LE (13)
DATA (12)
CLOCK (11)
Latch
Selector
Cntrl 22-Bit
Shift
Reg.
FIN2 (16)
FIN2# (15)
Prescaler
8/9 or
16/17
Pin Configuration
VCC1
VP1
DOPLL1
GND
FIN1
FIN1#
GND
OSC_IN
GND
FO/LD
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
TSSOP
Binary 4-Bit
Swallow Counter
GND (14)
VCC2
VP2
DOPLL2
GND
FIN2
FIN2#
GND
LE
DATA
CLOCK
19-Bit
Latch
Pwr-dwn
PLL1
15-Bit
Reference Counter
fr1
20-Bit Latch
20-Bit Latch
15-Bit
Reference Counter
fr2
19-Bit
Latch
Pwr-dwn
PLL2
Binary 11-Bit
Programmable Counter fp2
fr fp
Monitor
Output
Selector
Power
Control
Phase
Detector
Charge
Pump
GND (9)
GND (17)
VP2 (19)
FO/LD (10)
DOPLL2 (18)
NC
Vp1
DoPLL1
GND
Fin1
Fin1#
GND
OSC_IN
NC
1 21
2 20
3 19
4 18
5 (Top View) 17
6 16
7 15
8 14
9 13
NC
DoPLL2
GND
Fin2
Fin2#
GND
LE
DATA
NC
CSP
DoPLL1
GND
Fin1
Fin1#
GND
1
2
3
4
5
(Top View)
15 GND
14 Fin2
13 Fin2#
12 GND
11 LE
MLF
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
February 12, 2001. Rev. **


Cypress Semiconductor Electronic Components Datasheet

CYW2331 Datasheet

Dual Serial Input PLL

No Preview Available !

PRELIMINARY
CYW2331
Pin Definitions
Pin Name
Pin
No.
(TSSOP)
VCC1
1
Pin
No.
(CSP)
24
Pin
No.
(MLF)
19
VP1
DOPLL1
www.DataSheet4U.com
FIN1
FIN1#
2 2 20
3 31
5 53
6 64
OSC_IN
FO/LD
8 86
10 11 8
CLOCK
DATA
LE
11 12 9
12 14 10
13 15 11
FIN2#
FIN2
DOPLL2
VP2
VCC2
GND
N/C
15 17 13
16 18 14
18 20 16
19 22 17
20 23 18
4, 7, 9,
14, 17
N/A
4, 7,
10,
16, 19
1, 9,
13, 21
2, 5, 7,
12, 15
N/A
Pin
Type
P
P
O
I
I
I
O
I
I
I
I
I
O
P
P
G
N/C
Pin Description
Power Supply Connection for PLL1 and PLL2: When power
is removed from both the VCC1 and VCC2 pins, all latched data
is lost.
PLL1 Charge Pump Rail Voltage: This voltage accommodates
VCO circuits with tuning voltages higher than the VCC of PLL1.
PLL1 Charge Pump Output: The phase detector gain is IP/2π.
Sense polarity can be reversed by setting the FC bit in software
(via the Shift Register).
Input to PLL1 Prescaler: Maximum frequency 2.0 GHz.
Complementary Input to PLL1 Prescaler: A bypass capacitor
should be placed as close as possible to this pin and must be
connected directly to the ground plane.
Oscillator Input: This input has a VCC/2 threshold and CMOS
logic level sensitivity.
Lock Detect Pin of PLL1 Section: This output is HIGH when
the loop is locked. It is multiplexed to the output of the program-
mable counters or reference dividers in the test program mode.
(Refer to Table 3 for configuration.)
Data Clock Input: One bit of data is loaded into the Shift Reg-
ister on the rising edge of this signal.
Serial Data Input
Load Enable: On the rising edge of this signal, the data stored
in the Shift Register is latched into the reference counter and
configuration controls, PLL1 or PLL2 depending on the state of
the control bits.
Complementary Input to PLL2 Prescaler: A bypass capacitor
should be placed as close as possible to this pin and must be
connected directly to the ground plane.
Input to PLL2 Prescaler: Maximum frequency 600 MHz.
PLL2 Charge Pump Output: The phase detector gain is IP/2π.
Sense polarity can be reversed by setting the FC bit in software
(via the Shift Register).
PLL2 Charge Pump Rail Voltage: This voltage accommodates
VCO circuits with tuning voltages higher than the VCC of PLL2.
Power Supply Connections for PLL1 and PLL2: When power
is removed from both the VCC1 and VCC2 pins, all latched data
is lost.
Analog and Digital Ground Connections: This pin must be
grounded.
No Connect
2


Part Number CYW2331
Description Dual Serial Input PLL
Maker Cypress Semiconductor
Total Page 12 Pages
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