GVT71256E18
Key Features
- All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK)
- Asynchronous inputs include the Output Enable (OE) and Burst Mode Control (MODE), and Sleep Mode Control (ZZ)
- The data outputs (DQ), enabled by OE, are also asynchronous
- Addresses and chip enables are registered with either Address Status Processor (ADSP) or Address Status Controller (ADSC) input pins
- Subsequent burst addresses can be internally generated as controlled by the Burst Advance pin (ADV)
- Address, data inputs, and write controls are registered on-chip to initiate a self-timed Write cycle
- Write cycles can be one to four bytes wide as controlled by the write control inputs
- Individual byte write allows individual byte to be written
- WEL controls DQ1-DQ8 and DQP1
- WEH controls DQ9-DQ16 and DQP2
